Renesas RX100 Series User Manual page 23

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24. I C-bus Interface (RIICa) ............................................................................................................. 724
24.1 Overview ........................................................................................................................................... 724
24.2 Register Descriptions ......................................................................................................................... 727
2
24.2.1 I C-bus Control Register 1 (ICCR1) ........................................................................................ 727
2
24.2.2 I C-bus Control Register 2 (ICCR2) ........................................................................................ 729
2
24.2.3 I C-bus Mode Register 1 (ICMR1) .......................................................................................... 733
2
24.2.4 I C-bus Mode Register 2 (ICMR2) .......................................................................................... 734
2
24.2.5 I C-bus Mode Register 3 (ICMR3) .......................................................................................... 736
2
24.2.6 I C-bus Function Enable Register (ICFER) ............................................................................. 738
2
24.2.7 I C-bus Status Enable Register (ICSER) ................................................................................. 740
2
24.2.8 I C-bus Interrupt Enable Register (ICIER) .............................................................................. 742
2
24.2.9 I C-bus Status Register 1 (ICSR1) ........................................................................................... 744
2
24.2.10 I C-bus Status Register 2 (ICSR2) ........................................................................................... 747
24.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2) .................................................................... 750
24.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2) .................................................................... 751
2
24.2.13 I C-bus Bit Rate Low-Level Register (ICBRL) ....................................................................... 752
2
24.2.14 I C-bus Bit Rate High-Level Register (ICBRH) ...................................................................... 753
2
24.2.15 I C-bus Transmit Data Register (ICDRT) ................................................................................ 755
2
24.2.16 I C-bus Receive Data Register (ICDRR) ................................................................................. 755
2
24.2.17 I C-bus Shift Register (ICDRS) ............................................................................................... 755
24.3 Operation ........................................................................................................................................... 756
24.3.1 Communication Data Format ................................................................................................... 756
24.3.2 Initial Settings ........................................................................................................................... 757
24.3.3 Master Transmit Operation ....................................................................................................... 758
24.3.4 Master Receive Operation ........................................................................................................ 761
24.3.5 Slave Transmit Operation ......................................................................................................... 767
24.3.6 Slave Receive Operation .......................................................................................................... 770
24.4 SCL Synchronization Circuit ............................................................................................................. 772
24.5 SDA Output Delay Function ............................................................................................................. 773
24.6 Digital Noise Filter Circuit ................................................................................................................ 774
24.7 Address Match Detection .................................................................................................................. 775
24.7.1 Slave-Address Match Detection ............................................................................................... 775
24.7.2 Detection of the General Call Address ..................................................................................... 777
24.7.3 Device-ID Address Detection ................................................................................................... 778
24.7.4 Host Address Detection ............................................................................................................ 780
24.8 Automatic Low-Hold Function for SCL ........................................................................................... 781
24.8.1 Function to Prevent Wrong Transmission of Transmit Data .................................................... 781
24.8.2 NACK Reception Transfer Abort Function .............................................................................. 782
24.8.3 Function to Prevent Failure to Receive Data ............................................................................ 783
24.9 Arbitration-Lost Detection Functions ................................................................................................ 785
24.9.1 Master Arbitration-Lost Detection (MALE Bit) ...................................................................... 785