Renesas RX100 Series User Manual page 16

19.2.7 Timer Compare Match Clear Register (TCNTCMPCLR) ....................................................... 348
19.2.8 Timer Interrupt Enable Register (TIER) .................................................................................. 349
19.2.9 Timer Status Register (TSR) .................................................................................................... 352
19.2.10 Timer Buffer Operation Transfer Mode Register (TBTM) ...................................................... 353
19.2.11 Timer Input Capture Control Register (TICCR) ...................................................................... 354
19.2.12 Timer Counter (TCNT) ............................................................................................................ 355
19.2.13 Timer Longword Counter (TCNTLW) ..................................................................................... 355
19.2.14 Timer General Register (TGR) ................................................................................................. 356
19.2.15 Timer Longword General Registers (TGRALW, TGRBLW) .................................................. 356
19.2.16 Timer Start Registers (TSTRA, TSTR) .................................................................................... 357
19.2.17 Timer Synchronous Register (TSYRA) ................................................................................... 359
19.2.18 Timer Counter Synchronous Start Register (TCSYSTR) ......................................................... 360
19.2.19 Timer Read/Write Enable Register (TRWERA) ...................................................................... 361
19.2.20 Timer Output Master Enable Register (TOERA) ..................................................................... 362
19.2.21 Timer Output Control Register 1 (TOCR1A) ........................................................................... 363
19.2.22 Timer Output Control Register 2 (TOCR2A) ........................................................................... 365
19.2.23 Timer Output Level Buffer Register (TOLBRA) ..................................................................... 368
19.2.24 Timer Gate Control Register A (TGCRA) ............................................................................... 369
19.2.25 Timer Subcounter (TCNTSA) .................................................................................................. 370
19.2.26 Timer Period Data Register (TCDRA) ..................................................................................... 370
19.2.27 Timer Period Buffer Register (TCBRA) .................................................................................. 371
19.2.28 Timer Dead Time Data Register (TDDRA) ............................................................................. 371
19.2.29 Timer Dead Time Enable Register (TDERA) .......................................................................... 372
19.2.30 Timer Buffer Transfer Set Register (TBTERA) ....................................................................... 373
19.2.31 Timer Waveform Control Register (TWCRA) ......................................................................... 374
19.2.32 Noise Filter Control Register n (NFCRn) (n = 0 to 4, C) ......................................................... 375
19.2.33 Noise Filter Control Register 5 (NFCR5) ................................................................................. 377
19.2.34 Timer A/D Converter Start Request Control Register (TADCR) ............................................ 378
19.2.35 Timer A/D Converter Start Request Cycle Set Registers (TADCORA, TADCORB) ............. 380
19.2.36 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA, TADCOBRB) .................................................................................................. 380
19.2.37 Timer Interrupt Skipping Mode Register (TITMRA) .............................................................. 381
19.2.38 Timer Interrupt Skipping Set Register 1 (TITCR1A) .............................................................. 382
19.2.39 Timer Interrupt Skipping Counter 1 (TITCNT1A) .................................................................. 383
19.2.40 Timer Interrupt Skipping Set Register 2 (TITCR2A) .............................................................. 384
19.2.41 Timer Interrupt Skipping Counter 2 (TITCNT2A) .................................................................. 385
19.2.42 A/D Conversion Start Request Select Register 0 (TADSTRGR0) ........................................... 386
19.3 Operation ........................................................................................................................................... 387
19.3.1 Basic Functions ......................................................................................................................... 387
19.3.2 Synchronous Operation ............................................................................................................ 393
19.3.3 Buffer Operation ....................................................................................................................... 395