Buses; Overview - Renesas RX100 Series User Manual

RX13T Group
15.

Buses

15.1

Overview

Table 15.1 lists the bus specifications, Figure 15.1 shows the bus configuration, and Table 15.2 lists the addresses
assigned to each bus.
Table 15.1 Bus Specifications
Bus Type
CPU bus Instruction bus
Operand bus
Memory bus Memory bus 1
Memory bus 2
Internal main Internal main bus 1
buses
Internal main bus 2
Internal Internal peripheral
peripheral bus 1
buses
Internal peripheral
bus 2
Internal peripheral
bus 3
Internal peripheral
bus 6
P/E: Programming/Erasure
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
 Connected to the CPU for instructions
 Connected to on-chip memory (RAM, ROM)
 Operates in synchronization with the system clock (ICLK)
 Connected to the CPU (for operands)
 Connected to on-chip memory (RAM, ROM)
 Operates in synchronization with the system clock (ICLK)
 Connected to RAM
 Connected to ROM
 Connected to the CPU
 Operates in synchronization with the system clock (ICLK)
 Connected to the DTC
 Connected to on-chip memory (RAM, ROM)
 Operates in synchronization with the system clock (ICLK)
 Connected to peripheral modules (DTC, interrupt controller, and bus error monitoring section)
 Operates in synchronization with the system clock (ICLK)
 Connected to peripheral modules
 Operates in synchronization with the peripheral module clock (PCLKB, PCLKD)
 Connected to peripheral modules (CMPC)
 Operates in synchronization with the peripheral module clock (PCLKB)
 Connected to ROM (P/E) and E2 DataFlash
 Operates in synchronization with the FlashIF clock (FCLK)
15. Buses
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