Flash Control Register (Fcr) - Renesas RX100 Series User Manual

RX13T Group
31.4.9

Flash Control Register (FCR)

Address(es): FLASH.FCR 007F FF85h
b7 b6
OPST STOP
0 0
Value after reset:
Bit Symbol Bit Name
b3 to b0 CMD[3:0] Software Command Setting
b4 DRC Data Read Completion
b5 — Reserved
b6 STOP Forced Processing Stop
b7 OPST Processing Start
Note 1. This does not include set the FCR register to 00h when the FSTATR1.FRDY flag is 1.
Data can be written to the FCR register when in ROM P/E mode and the ROM can be programmed/erased or in E2
DataFlash P/E mode.
This register is initialized by a reset or setting the FRESETR.FRESET bit to 1. Data cannot be written to this register
while the FRESETR.FRESET bit is 1.
Note that this register cannot be initialized by the FRESETR.FRESET bit while a software command is being executed.
CMD[3:0] Bits (Software Command Setting)
These bits are used to set a software command (program, blank check, block erase, or unique ID read).
The function of each command is described below.
[Program]
 Write the value set in registers FWBH and FWBL to the address set in registers FSARH and FSARL.
[Blank check]
 Check whether there is data in the area from the address set in registers FSARH and FSARL to the address set in
registers FEARH and FEARL. Confirm that data is not programmed in the area. This command does not guarantee
whether the area remains erased.
[Block erase]
 Erase consecutive areas specified in the flash memory by the blocks. Set the beginning address of the block in
registers FSARH and FSARL and the end address in registers FEARH and FEARL.
[Unique ID read]
 When executing the unique ID read after setting registers FSARH, FSARL, FEARH, and FEARL to 00h, 0850h,
00h, and 086Fh, respectively, the unique ID is stored in registers FRBH and FRBL sequentially.
DRC Bit (Data Read Completion)
This bit is used with the unique ID read command to control the state of the sequencer.
When issuing the unique ID read command with this bit set to 0, data is read from the address set in registers FSARH and
FSARL, and the data is stored in registers FRBH and FRBL.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— DRC CMD[3:0]
0 0 0 0
b1 b0
0 0
Description
b3 b0
0 0 0 1: Program
0 0 1 1: Blank check
0 1 0 0: Block erase
0 1 0 1: Unique ID read
Settings other than above are prohibited.*
0: Start data read.
1: Complete data read.
This bit is read as 0. The write value should be 0.
When this bit is set to 1, the processing being executed can be
forcibly stopped.
0: Processing stops.
1: Processing starts.
31. Flash Memory (FLASH)
R/W
R/W
1
R/W
R/W
R/W
R/W
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