Renesas RX100 Series User Manual page 808

RX13T Group
Table 26.1 Specifications of 12-Bit A/D Converter (1/2)
Item
Number of units
Input channels
Extended analog function
A/D conversion method
Resolution
Conversion time
A/D conversion clock
Data registers
Operating modes
Conditions for A/D
conversion start
Functions
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
One unit (S12AD)
Eight channels for S12AD
Internal reference voltage
Successive approximation method
12 bits
1.4 μs per channel
(when A/D conversion clock ADCLK = 32 MHz)
Peripheral module clock PCLK*
should be one of the following.
PCLK to ADCLK frequency ratio = 1:1, 2:1, 4:1, 8:1
ADCLK is set using the clock generation circuit.
 Eight registers for analog input, 1 for A/D-converted data duplication in double trigger mode, and 2 for A/
D-converted data duplication during extended operation in double trigger mode.
 One register for internal reference
 One register for self-diagnosis
 The results of A/D conversion are stored in 12-bit A/D data registers.
 12-bit accuracy output for the results of A/D conversion
 The value obtained by adding up A/D-converted results is stored as a value in the number of bit for
conversion accuracy + 2 bits/4 bits*
 Double trigger mode (selectable in single scan and group scan modes):
The first piece of A/D-converted analog-input data on one selected channel is stored in the data register
for the channel, and the second piece is stored in the duplication register.
 Extended operation in double trigger mode (available for specific triggers):
A/D-converted analog-input data on one selected channel is stored in the duplication register that is
prepared for each type of trigger.
 Single scan mode:
A/D conversion is performed only once on the analog inputs arbitrarily selected.
A/D conversion is performed only once on the internal reference voltage.
 Continuous scan mode:
A/D conversion is performed repeatedly on the analog inputs arbitrarily selected.
 Group scan mode:
Two (groups A and B) or three (groups A, B, and C) can be selected as the number of the groups to be
used.
Only the combination of groups A and B can be selected when the number of the groups is two.
Analog inputs arbitrarily selected are divided into two groups (group A and B) or three groups (group A,
B, and C), and A/D conversion of the analog input selected on a group basis is performed only once.
The conditions for scanning start of groups A, B, and C (synchronous trigger) can be independently
selected, thus allowing A/D conversion of each group to be started independently.
 Group scan mode (when group priority control selected):
If a priority-group trigger is input during scanning of the low-priority group, scan of the low-priority group
is stopped and scan of the priority group is started. The priority order is group A (highest) > group B >
group C (lowest).
Whether or not to restart scanning of the low-priority group after processing for the high-priority group
completes, is selectable. Rescan can also be set to start either from the beginning of the selected
channel or the channel on which A/D conversion is not completed.
 Software trigger
 Synchronous trigger
Trigger by the multi-function timer pulse unit (MTU)
 Asynchronous trigger
A/D conversion can be triggered by the external trigger ADTRG0# pin.
 Channel-dedicated sample-and-hold function (three channels)
 Input signal amplification function of the programmable gain amplifier (3 channels)
 Variable sampling state count (settable for each channel)
 Self-diagnosis of 12-bit A/D converter
 Selectable A/D-converted value addition mode or average mode
 Analog input disconnection detection assist function (discharge function/precharge function)
 Double trigger mode (duplication of A/D conversion data)
 Automatic clear function of A/D data registers
1 and A/D conversion clock ADCLK*
2
in the A/D data registers in A/D-converted value addition mode.
26. 12-Bit A/D Converter (S12ADF)
1 can be set so that the frequency ratio
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