Selectable Timing For Sampling Data Received Through Rxdx12 - Renesas RX100 Series User Manual

RX13T Group
23.10.7

Selectable Timing for Sampling Data Received through RXDX12

The extended serial mode control section provides a way of adjusting the timing for the sampling of data received
through the RXDX12 pin by setting the CR2.RTS[1:0] bits to select the rising edges of 8th, 10th, 12th, or 14th cycle of
the base clock. If the value of the SEMR.ABCS bit is 1, the bits select the rising edges of 4th, 5th, 6th, or 7th cycle of the
base clock. Figure 23.71 shows timing for the sampling of data received through RXDX12.
Base clock
RXDX12 receive data
RTS[1:0] = 00b
RTS[1:0] = 01b
RTS[1:0] = 10b
RTS[1:0] = 11b
The above diagram assumes the following:
SEMR.ABCS = 0
Figure 23.71 Timing for Sampling of Data Received through RXDX12
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
23. Serial Communications Interface (SCIg, SCIh)
16 clocks
8 clocks
10 clocks
12 clocks
14 clocks
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