Interrupt Request Enable Register M (Ierm) (M = 02H To 1Fh) - Renesas RX100 Series User Manual

RX13T Group
14.2.2

Interrupt Request Enable Register m (IERm) (m = 02h to 1Fh)

Address(es): ICU.IER02 0008 7202h to ICU.IER1F 0008 721Fh
b7 b6
IEN7 IEN6
Value after reset: 0 0
Bit Symbol
b0 IEN0
b1 IEN1
b2 IEN2
b3 IEN3
b4 IEN4
b5 IEN5
b6 IEN6
b7 IEN7
Note: Write 0 to the bit that corresponds to the vector number for reservation. These bits are read as 0.
IENj Bit (Interrupt Request Enable j) (j = 0 to 7)
When an IENj bit is 1, the corresponding interrupt request will be output to the destination selected for the request.
When an IENj bit is 0, the corresponding interrupt request will not be output to the destination selected for the request.
The setting of an IENj bit does not affect the IRn.IR flag (n = interrupt vector number). Even if the corresponding IENj
bit is 0, the IR flag value changes according to the descriptions in section 14.2.1, Interrupt Request Register n (IRn)
(n = interrupt vector number) .
The IERm.IENj bit is set for each request source (vector number).
For the correspondence between interrupt sources and IERm.IENj bits, see Table 14.3, Interrupt Vector Table .
For the procedure for setting IERm.IENj bits during the selection of destinations for interrupt requests, refer to section
14.4.3, Selecting Interrupt Request Destinations .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
IEN5 IEN4 IEN3 IEN2
0 0 0 0
Bit Name
Interrupt Request Enable 0
Interrupt Request Enable 1
Interrupt Request Enable 2
Interrupt Request Enable 3
Interrupt Request Enable 4
Interrupt Request Enable 5
Interrupt Request Enable 6
Interrupt Request Enable 7
b1 b0
IEN1 IEN0
0 0
Description
0: Interrupt request is disabled
1: Interrupt request is enabled
14. Interrupt Controller (ICUb)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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