Renesas RX100 Series User Manual page 539

RX13T Group
specified in the POECR5 register, the ICSRn.POEmF flag (n = 1, 4; m = 0, 10), or POECMPFR.CnFLAG flag (n = 0 to
2), is set to 1.
MTU0A1ZE Bit (MTIOC0A (PD3) Pin High-Impedance Enable)
This bit specifies whether to switch the MTIOC0A output of PD3 to the high-impedance state when any of the
ICSR3.POE8F flag, SPOER.MTUCH0HIZ bit, and ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally
specified in the POECR5 register, the ICSRn.POEmF flag (n = 1, 4; m = 0, 10), or POECMPFR.CnFLAG flag (n = 0 to
2), is set to 1.
MTU0B1ZE Bit (MTIOC0B (PD4) Pin High-Impedance Enable)
This bit specifies whether to switch the MTIOC0B output of PD4 to the high-impedance state when any of the
ICSR3.POE8F flag, SPOER.MTUCH0HIZ bit, and ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally
specified in the POECR5 register, the ICSRn.POEmF flag (n = 1, 4; m = 0, 10), or POECMPFR.CnFLAG flag (n = 0 to
2), is set to 1.
MTU0C1ZE Bit (MTIOC0C (PD5) Pin High-Impedance Enable)
This bit specifies whether to switch the MTIOC0C output of PD5 to the high-impedance state when any of the
ICSR3.POE8F flag, SPOER.MTUCH0HIZ bit, and ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally
specified in the POECR5 register, the ICSRn.POEmF flag (n = 1, 4; m = 0, 10), or POECMPFR.CnFLAG flag (n = 0 to
2), is set to 1.
MTU0D1ZE Bit (MTIOC0D (PD6) Pin High-Impedance Enable)
This bit specifies whether to switch the MTIOC0D output of PD6 to the high-impedance state when any of the
ICSR3.POE8F flag, SPOER.MTUCH0HIZ bit, and ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally
specified in the POECR5 register, the ICSRn.POEmF flag (n = 1, 4; m = 0, 10), or POECMPFR.CnFLAG flag (n = 0 to
2), is set to 1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
20. Port Output Enable 3 (POE3C)
Page 539 of 1041