Multi-Processor Communications Function - Renesas RX100 Series User Manual

RX13T Group
23.4

Multi-Processor Communications Function

Using the multi-processor communication functions enables to transmit and receive data by sharing a communication
line between multiple processors by using asynchronous serial communication in which the multi-processor bit is added.
In multi-processor communication, a unique ID code is allocated to each receiving station. Serial communication cycles
consist of an ID transmission cycle to specify the receiving station and a data transmission cycle to transmit data to the
specified receiving station. The multi-processor bit is used to distinguish between the ID transmission cycle and the data
transmission cycle. When the multi-processor bit is set to 1, it indicates the ID transmission cycle and when the multi-
processor bit is set to 0, it indicates the data transmission cycle. Figure 23.17 shows an example of communication
between processors by using a multi-processor format. First, a transmitting station transmits communication data in
which the multi-processor bit set to 1 is added to the ID code of the receiving station. Next, the transmitting station
transmits the communication data in which the multi-processor bit set to 0 is added to the transmit data. Upon receiving
the communication data in which the multi-processor bit is set to 1, the receiving station compares the received ID with
the ID of the receiving station itself and if the two match, receives the communication data that is subsequently
transmitted. If the received ID does not match with the ID of the receiving station, the receiving station skips the
communication data until again receiving the communication data in which the multi-processor bit is set to 1.
For supporting this function, the SCI provides the SCR.MPIE bit. When the MPIE bit is set to 1, transfer of receive data
from the RSR register to the RDR register (the RDRH and RDRL registers when 9-bit data length is selected), detection
of a receive error, and setting the respective status flags RDRF, ORER, and FER in the SSR register are disabled until
reception of data in which the multi-processor bit is set to 1. Upon receiving a reception character in which the multi-
processor bit is set to 1, the SSR.MPB bit is set to 1 and the SCR.MPIE bit is automatically cleared, thus returning to a
normal reception operation. During this time, an RXI interrupt is generated if the SCR.RIE bit is 1.
When the multi-processor format is specified, specification of the parity bit is disabled. Apart from this, there is no
difference from the operation in the normal asynchronous mode. A clock which is used for the multi-processor
communication is also the same as the clock used in the normal asynchronous mode.
Transmitting
Serial data
MPB: Multi-processor bit
Figure 23.17 An Example of Communication using the Multi-Processor Format
(Example of Transmission of Data AAh to Receiving Station A)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
station
Receiving Receiving
station A station B
(ID = 01) (ID = 02)
(MPB = 1)
01h
ID transmission cycle =
specification of a receiving station
23. Serial Communications Interface (SCIg, SCIh)
Communication line
Receiving
station C
(ID = 03)
AAh
(MPB = 1)
Data transmission cycle = data
transmission to the receiving
station specified by ID
Receiving
station D
(ID = 04)
(MPB = 0)
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