Clock Synchronization - Renesas RX100 Series User Manual

RX13T Group
23.7.2

Clock Synchronization

The SSCLn line may be placed at the low level in the case of a wait inserted by a slave device as the other side of
transfer. Setting the IICCSC bit in the SIMR2 register to 1 applies control to obtain synchronization when the levels of
the internal SSCLn clock signal and the level being input on the SSCLn pin differ.
When the IICCSC bit in the SIMR2 register is set to 1, the level of the internal SSCLn clock signal changes from low to
high, counting to determine the period at high level is stopped while the low level is being input on the SSCLn pin, and
counting to determine the period at high level starts after the transition of the input on the SSCLn pin to the high level.
The interval from this time until counting to determine the period at high level starts on the transition of the SSCLn pin to
the high level is the total of the delay of SSCLn output, delay for noise filtering of the input on the SSCLn pin (2 or 3
cycles of sampling clock for the noise filter), and delay for internal processing (1 or 2 cycles of PCLK). The period at
high level of the internal SSCLn clock is extended even if other devices are not placing the low level on the SSCLn line.
If the IICCSC bit in the SIMR2 register is 1, synchronization is obtained for the transmission and reception of data by
taking the logical AND of the input on the SSCLn pin and the internal SSCLn clock. If the IICCSC bit in the SIMR2
register is 0, synchronization with the internal SSCLn clock is obtained for the transmission and reception of data.
If a slave device inserts a period of waiting into the interval until the transition of the internal SSCLn clock signal from
the low to the high level after a request for the generation of a start, restart, or stop condition is issued, the time until
generation is prolonged by that period.
If a slave device inserts a period of waiting after the transition of the internal SSCLn clock signal from the low to the
high level, although the generation-completed interrupt is issued without stopping the period of waiting, generation of
the condition itself is not guaranteed. Figure 23.48 shows an example of operations to synchronize the clocks.
SSCLn output from the
other device
SSCLn line
Internal SSCLn clock
Clock driving transfer
internally
Figure 23.48 Example of Operations for Clock Synchronization
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
23. Serial Communications Interface (SCIg, SCIh)
Counting of the period
Counting of the period
at high level starts.
at low level starts.
Counting is stopped until the SSCLn
line being at the high level is
conveyed within the SCI.
Counting of the period
at high level starts.
Counting is stopped while the
SSCLn line is at the low level.
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