23.13 Usage Notes; Setting The Module Stop Function; Break Detection And Processing; Mark State And Sending Breaks - Renesas RX100 Series User Manual

RX13T Group

23.13 Usage Notes

23.13.1

Setting the Module Stop Function

Module stop control register B (MSTPCRB) is used to stop and start SCI operations. With the value after a reset, SCI
operations are stopped. Register access is enabled by releasing the module stop state. For details, refer to section 11,
Low Power Consumption .
23.13.2

Break Detection and Processing

When a framing error is detected, a break can be detected by reading the RXDn pin value directly. In a break, the input
from the RXDn pin becomes all 0s, and so the SSR.FER flag is set to 1 (framing error has occurred), and the SSR.PER
flag may also be set to 1 (parity error has occurred). When the SEMR.RXDESEL bit is 0, the SCI continues the receive
operation even after a break is received. Therefore, note that even if the FER flag is set to 0 (no framing error occurred),
it will be set to 1 again. When the SEMR.RXDESEL bit is 1, the SCI sets the SSR.FER flag to 1 and stops receiving
operation until a start bit of the next data frame is detected. If the SSR.FER flag is set to 0 at this time, the SSR.FER flag
retains 0 during the break. When the RXDn pin becomes high and the break ends, detecting the beginning of the start bit
at the first falling edge of the RXDn pin allows the SCI to start the receiving operation.
23.13.3

Mark State and Sending Breaks

When the SCR.TE bit is 0 (serial transmission is disabled), the TXDn pin becomes high-impedance. To forcibly set the
TXDn pin to mark or space state while the TE bit is 0, set the I/O port associated registers and switch the TXDn pin to
general output port.
For holding the communication line in the mark ("1") state until the TE bit is set to 1 (serial transmission is enabled), set
the corresponding bit in the PODR register to 1 for high output from general output port. To start communications, set the
TE bit to 1 and then the corresponding bit in the PMR register to 1.
To send a break (the space state for longer than a certain period of time) while data transmission, set the corresponding
bit in the PODR register to 0 (low output), and set the corresponding bit in the PMR register to 0 (general I/O port). Then
set the TE bit to 0 if necessary. When the TE bit is set to 0, the transmitter is initialized regardless of the current transmit
status.
23.13.4 Receive Error Flags and Transmit Operations (Clock Synchronous Mode and
Simple SPI Mode)
Transmission cannot be started when a receive error flag (ORER) in the SSR register is set to 1, even if data is written to
the TDR register. Be sure to set the receive error flags to 0 before starting transmission. Note also that the receive error
flags cannot be set to 0 even if the SCR.RE bit is set to 0 (serial reception is disabled).
23.13.5

Writing Data to the TDR Register

Data can be written to registers TDR, TDRH, and TDRL. However, if new data is written to registers TDR, TDRH, and
TDRL when transmit data is remaining in registers TDR, TDRH, and TDRL, the previous data in registers TDR, TDRH,
and TDRL is lost because it has not been transferred to the TSR register yet. Be sure to write transmit data to registers
TDR, TDRH, and TDRL in the TXI interrupt request handling routine.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
23. Serial Communications Interface (SCIg, SCIh)
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