Sci Initialization (Clock Synchronous Mode) - Renesas RX100 Series User Manual

RX13T Group
23.5.3

SCI Initialization (Clock Synchronous Mode)

Before transmitting and receiving data, start by writing the initial value 00h to the SCR register and then continue
through the procedure for SCI given in Figure 23.23 . Whenever the operating mode or transfer format is changed, the
SCR register must be initialized before the change is made.
Note that setting the SCR.RE bit to 0 initializes neither the ORER, FER, and PER flags in the SSR register nor the RDR
register.
Moreover, note that switching the value of the SCR.TE bit from 1 to 0 or 0 to 1 while the SCR.TIE bit is 1 leads to the
generation of a TXI interrupt request.
Start initialization
Set bits TIE, RIE, TE, RE, and TEIE in
SCR to 0
Set the I/O port functions
Set the SCR.CKE[1:0] bits
Set the SIMR1.IICM bit to 0
Set the SPMR.CKPH and CKPOL bits to 0
Set data transmission/reception format in
SMR, SCMR, and SEMR
Set a value in BRR
Set a value in MDDR
Set TE or RE bit in SCR to 1, and set TIE and
RIE bits in SCR
Transmission/reception
Note: In simultaneous transmit and receive operations, the TE and RE bits in SCR should both be set to
0 or 1 simultaneously.
Figure 23.23 Example of SCI Initialization Flowchart (Clock Synchronous Mode)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
23. Serial Communications Interface (SCIg, SCIh)
[ 1 ] Make I/O port settings to enable input and output
functions as required for TXDn, RXDn, and SCKn
pins.
[ 2 ] Set the clock selection in SCR.
When an internal clock is selected, the SCK pin
functions as the clock output pin.
[ 1 ]
[ 3 ] Set the SIMR1.IICM bit to 0.
Set the SPMR.CKPH and CKPOL bits to 0.
[ 2 ]
Step [3] can be skipped if the values have not been
changed from the initial values.
[ 3 ]
[ 4 ] Set the data transmission/reception format in SMR,
SCMR, and SEMR.
[ 4 ]
[ 5 ] Write a value corresponding to the bit rate to BRR.
This step is not necessary if an external clock is
used.
[ 5 ]
[ 6 ] Write the value obtained by correcting a bit rate
[ 6 ]
error in MDDR. This step is not necessary if the
BRME bit in SEMR is cleared to 0 or an external
clock is used.
[ 7 ]
[ 7 ] Set the TE bit or RE bit in SCR to 1. Also set the
TIE and RIE bits in SCR.
Setting the TE and RE bits allows TXDn and RXDn
to be used.
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