Port Output Enable Control Register 2 (Poecr2) - Renesas RX100 Series User Manual

RX13T Group
20.2.9

Port Output Enable Control Register 2 (POECR2)

Address(es): POE.POECR2 0008 C4CCh
b15 b14
— —
Value after reset: 0 0
Bit Symbol
b2 to b0 —
b7 to b3 —
b8 MTU4BDZE
b9 MTU4ACZE
b10 MTU3BDZE
b15 to b11 —
Note 1. Can be modified only once after a reset.
The POECR2 register controls high-impedance state of the MTU complementary PWM output pins (MTU3 and MTU4
pins).
MTU4BDZE Bit (MTIOC4B/MTIOC4D Pin High-Impedance Enable)
This bit specifies whether to switch the MTIOC4B output and MTIOC4D output to the high-impedance state when at
least one of the OCSR1.OSF1 flag, ICSR1.POE0F flag, SPOER.MTUCH34HIZ bit, ICSR6.OSTSTF flag (when the
OSTSTE bit is 1), or, as additionally specified in the POECR4 register, the ICSRn.POEmF flag (n = 3, 4; m = 8, 10), or
POECMPFR.CnFLAG flag (n = 0 to 2) is set to 1.
MTU4ACZE Bit (MTIOC4A/MTIOC4C Pin High-Impedance Enable)
This bit specifies whether to switch the MTIOC4A output and MTIOC4C output to the high-impedance state when at
least one of the OCSR1.OSF1 flag, ICSR1.POE0F flag, SPOER.MTUCH34HIZ bit, ICSR6.OSTSTF flag (when the
OSTSTE bit is 1), or, as additionally specified in the POECR4 register, the ICSRn.POEmF flag (n = 3, 4; m = 8, 10), or
POECMPFR.CnFLAG flag (n = 0 to 2) is set to 1.
MTU3BDZE Bit (MTIOC3B/MTIOC3D Pin High-Impedance Enable)
This bit specifies whether to switch the MTIOC3B output and MTIOC3D output to the high-impedance state when at
least one of the OCSR1.OSF1 flag, ICSR1.POE0F flag, SPOER.MTUCH34HIZ bit, ICSR6.OSTSTF flag (when the
OSTSTE bit is 1), or, as additionally specified in the POECR4 register, the ICSRn.POEmF flag (n = 3, 4; m = 8, 10), or
POECMPFR.CnFLAG flag (n = 0 to 2) is set to 1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
MTU3B
— — —
DZE
0 0 0 1
Bit Name
Reserved
Reserved
MTIOC4B/MTIOC4D Pin High-
Impedance Enable
MTIOC4A/MTIOC4C Pin High-
Impedance Enable
MTIOC3B/MTIOC3D Pin High-
Impedance Enable
Reserved
b9 b8 b7 b6
MTU4A MTU4B
— —
CZE DZE
1 1 0 0
Description
These bits are read as 0. The write value should be 1.
These bits are read as 0. The write value should be 0.
0: Does not switch the pins to high-impedance state.
1: Switch the pins to high-impedance state.
0: Does not switch the pins to high-impedance state.
1: Switch the pins to high-impedance state.
0: Does not switch the pins to high-impedance state.
1: Switch the pins to high-impedance state.
These bits are read as 0. The write value should be 0.
20. Port Output Enable 3 (POE3C)
b5 b4 b3 b2
— — — —
0 0 0 1
Page 540 of 1041
b1 b0
— —
1 1
R/W
R/W
R/W
1
R/W*
1
R/W*
R/W* 1
R/W