A/D Conversion In Extended Double Trigger Mode - Renesas RX100 Series User Manual

RX13T Group
26.3.2.7

A/D Conversion in Extended Double Trigger Mode

When the double-trigger mode is selected in single-scanning mode, with TRG4AN or TRG4BN selected in the
TRSA[5:0] bits of the A/D conversion start trigger select register (ADSTRGR), proceed with single scanning twice as
follows.
Self-diagnosis should be deselected, and the internal reference voltage A/D conversion select bit
(S12AD.ADEXICR.OCSA) should be set to 0.
Duplication of A/D conversion data is enabled by setting the channel numbers to be duplicated to the
ADCSR.DBLANS[4:0] bits and setting the ADCSR.DBLE bit to 1. When the ADCSR.DBLE bit is set to 1, channel
selection using the ADANSA0 register is invalid. In extended double trigger mode, the ADCSR.EXTRG bit should be
set to 0, and the ADCSR.TRGE bit should be set to 1. Software trigger should not be used.
(1) When the ADCSR.ADST bit is set to 1 (A/D conversion start) by TRG4AN input, A/D conversion is started on the
single channel selected by the ADCSR.DBLANS[4:0] bits.
(2) When A/D conversion is completed, the A/D conversion result is stored into the corresponding A/D data register
(ADDRy) and A/D data-duplication register A (ADDBLDRA).
(3) The ADCSR.ADST bit is automatically cleared to 0 and the 12-bit A/D converter enters a wait state. Here, a scan
end interrupt request is not generated irrespective of the ADCSR.ADIE bit setting (interrupt generation upon
scanning completion enabled).
(4) When the ADCSR.ADST bit is set to 1 (A/D conversion start) by TRG4BN input, A/D conversion is started on the
single channel selected by the ADCSR.DBLANS[4:0] bits.
(5) When A/D conversion is completed, the A/D conversion result is stored into A/D data duplication register
(ADDBLDR) and A/D data duplication register B (ADDBLDRB).
(6) If the ADCSR.ADIE bit is 1 (interrupt generation upon scanning completion enabled), a scan end interrupt request
is generated.
(7) The ADCSR.ADST bit remains 1 (A/D conversion start) during A/D conversion, and is automatically cleared to 0
when A/D conversion is completed. Then the 12-bit A/D converter enters a wait state.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
26. 12-Bit A/D Converter (S12ADF)
Page 845 of 1041