Timer Control Register (Tcr); Timer Mode Register (Tmr) - Renesas RX100 Series User Manual

RX13T Group
23.2.36

Timer Control Register (TCR)

Address(es): SCI12.TCR 0008 B330h
b7 b6
— —
Value after reset: 0 0
Bit Symbol Bit Name
b0 TCST Timer Count Start
b7 to b1 — Reserved
23.2.37

Timer Mode Register (TMR)

Address(es): SCI12.TMR 0008 B331h
b7 b6
—
Value after reset: 0 0
Bit Symbol
b1, b0 TOMS[1:0]
b2 —
b3 TWRC
b6 to b4 TCSS[2:0]
b7 —
Note 1. Rewrite the TOMS[1:0] and TCSS[2:0] bits only when the timer is stopped (TCST = 0).
TWRC Bit (Counter Write Control)
This bit determines whether a value written to TPRE or TCNT is written to the reload register only or is written to both
the reload register and the counter.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
Description
0: Stops the timer counting
1: Starts the timer counting
These bits are read as 0. The write value should be 0.
b5 b4 b3 b2
TCSS[2:0] TWRC —
0 0 0 0
Bit Name
Timer Operating Mode Select*
Reserved
Counter Write Control
Timer Count Clock Source Select*
Reserved
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
— TCST
0 0
b1 b0
TOMS[1:0]
0 0
Description
1
b1 b0
0 0: Timer mode
0 1: Break Field low width determination mode
1 0: Break Field low width output mode
1 1: Setting prohibited
This bit is read as 0. The write value should be 0.
0: Data is written to the reload register and counter
1: Data is written to the reload register only
1
b6 b4
0 0 0: PCLK
0 0 1: PCLK/2
0 1 0: PCLK/4
0 1 1: PCLK/8
1 0 0: PCLK/16
1 0 1: PCLK/32
1 1 0: PCLK/64
1 1 1: PCLK/128
This bit is read as 0. The write value should be 0.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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