Renesas RX100 Series User Manual page 343

RX13T Group
Table 19.22 TIORL (MTU0)
Bit 3 Bit 2 Bit 1
IOC[3] IOC[2] IOC[1]
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 1 x
x: Don't care
Note 1. When the MTU0.TMDR1.BFB bit is set to 1 and MTU0.TGRC register is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
Note 2. When PCLKB/1 is selected as the count clock for MTU1, MTU0 input capture is not generated. Do not select PCLKB/1 as the
count clock for MTU1.
Table 19.23 TIOR (MTU1)
Bit 3 Bit 2 Bit 1
IOA[3] IOA[2] IOA[1]
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 1 x
x: Don't care
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Bit 0 Description
IOC[0] TGRC Register Function
0 Output compare register*
1
0
1
0
1
0
1
0 Input capture register*
1
x
x
Bit 0 Description
TGRA/TGRALW Register
IOA[0] Function
0 Output compare register
1
0
1
0
1
0
1
0 Input capture register
1
x
x
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
MTIOC0C Pin Function
1
Output prohibited
Initial output is low.
Low output at compare match.
Initial output is low.
High output at compare match.
Initial output is low.
Toggle output at compare match.
Output prohibited
Initial output is high.
Low output at compare match.
Initial output is high.
High output at compare match.
Initial output is high.
Toggle output at compare match.
1
Input capture at rising edge.
Input capture at falling edge.
Input capture at both edges.
Capture input source is the clock source for counting in MTU1.
Input capture on counting up or down by MTU1.TCNT (LWA = 0) or
MTU1.TCNTLW (LWA = 1).*
MTIOC1A Pin Function
Output prohibited
Initial output is low.
Low output at compare match.
Initial output is low.
High output at compare match.
Initial output is low.
Toggle output at compare match.
Output prohibited
Initial output is high.
Low output at compare match.
Initial output is high.
High output at compare match.
Initial output is high.
Toggle output at compare match.
Input capture at rising edge.
Input capture at falling edge.
Input capture at both edges.
Input capture at generation of MTU0.TGRA compare match/input
capture.
2
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