23.12 Interrupt Sources; Buffer Operations For Txi And Rxi Interrupts; Interrupts In Asynchronous Mode, Clock Synchronous Mode, And Simple Spi Mode - Renesas RX100 Series User Manual

RX13T Group

23.12 Interrupt Sources

23.12.1

Buffer Operations for TXI and RXI Interrupts

If the conditions for a TXI and RXI interrupt are satisfied while the interrupt status flag in the interrupt controller is 1, the
SCI does not output the interrupt request but retains it internally (with a capacity for retention of one request per source).
When the value of the interrupt status flag in the interrupt controller becomes 0, the interrupt request retained within the
SCI is output. The internally retained interrupt request is automatically discarded once the actual interrupt is output.
Clearing of the corresponding interrupt enable bit (the TIE or RIE bit in the SCR) can also be used to discard an
internally retained interrupt request.
23.12.2 Interrupts in Asynchronous Mode, Clock Synchronous Mode, and Simple SPI
Mode
Table 23.31 lists interrupt sources in asynchronous mode, clock synchronous mode, and simple SPI mode. Individual
interrupt sources can be enabled or disabled with the enable bits in the SCR register.
If the SCR.TIE bit is 1, a TXI interrupt request is generated when transmit data is transferred from the TDR or TDRL
1
register * to the TSR. A TXI interrupt request can also be generated by setting the SCR.TE bit to 1 after setting the
SCR.TIE bit to 1 or by using a single instruction to set the SCR.TE and SCR.TIE bit to 1 at the same time. A TXI
interrupt request can activate the DTC to handle data transfer.
A TXI interrupt request is not generated by setting the SCR.TE bit to 1 while the setting of the SCR.TIE bit is 0 or by
setting the SCR.TIE bit to 1 while the setting of the SCR.TE bit is 1. *
When new data is not written by the time of transmission of the last bit of the current transmit data and the setting of the
SCR.TEIE bit is 1, the SSR.TEND flag becomes 1 and a TEI interrupt request is generated. Furthermore, when the
setting of the SCR.TE bit is 1, the SSR.TEND flag retains the value 1 until further transmit data are written to the TDR or
1
TDRL register *
, and setting the SCR.TEIE bit to 1 leads to the generation of a TEI interrupt request.
Writing data to the TDR or TDRL register *
of the TEI interrupt request.
If the SCR.RIE bit is 1, an RXI interrupt request is generated when received data is stored in the RDR. An RXI interrupt
request can activate the DTC to handle data transfer.
Setting of any from among the ORER, FER, and PER flags in the SSR to 1 while the SCR.RIE bit is 1 leads to the
generation of an ERI interrupt request. An RXI interrupt request is not generated at this time. Clearing all three flags
(ORER, FER, and PER) leads to discarding of the ERI interrupt request.
Note 1. In the case where asynchronous mode and 9-bit data length are selected
Note 2. To temporarily disable TXI interrupts at the time of transmission of the last of the data and so on when you wish a
new round of transmission to start after handling of the transmission-completed interrupt, control disabling and
enabling of the interrupt by using the interrupt request enable bit in the interrupt controller rather than using the
SCR.TIE bit. This can prevent the suppression of TXI interrupt requests in the transfer of new data.
Table 23.31 Interrupt Sources
Name Interrupt Source
ERI Receive error
RXI Receive data full
TXI Transmit data empty
TEI Transmit end
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
23. Serial Communications Interface (SCIg, SCIh)
1
leads to clearing of the SSR.TEND flag and, after a certain time, discarding
Interrupt Flag
ORER, FER, or PER
RDRF
TDRE
TEND
2
DTC Activation
Not possible
Possible
Possible
Not possible
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