Block Transfer Mode - Renesas RX100 Series User Manual

RX13T Group
For communications with IC cards of the direct convention type and inverse convention type, follow the procedure
below.
(1) Direct Convention Type
For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with
LSB first as the start character, as shown in Figure 23.34 . Therefore, data in the start character in the figure is 3Bh.
When using the direct convention type, write 0 to both the SDIR and SINV bits in the SCMR register. Write 0 to the PM
bit in the SMR register in order to use even parity, which is prescribed by the smart card standard.
Figure 23.34 Direct Convention (SDIR in SCMR = 0, SINV in SCMR = 0, PM in SMR = 0)
(2) Inverse Convention Type
For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred
with MSB first as the start character, as shown in Figure 23.35 . Therefore, data in the start character in the figure is 3Fh.
When using the inverse convention type, write 1 to both the SDIR and SINV bits in the SCMR register. The parity bit is
logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the
SINV bit of the this MCU only inverts data bits D7 to D0, write 1 to the PM bit in the SMR register to invert the parity
bit for both transmission and reception.
Figure 23.35 Inverse Convention (SDIR in SCMR = 1, SINV in SCMR = 1, PM in SMR = 1)
23.6.3

Block Transfer Mode

Block transfer mode is different from non-block transfer mode in the following respects.
 Even if a parity error is detected during reception, no error signal is output. Since the PER bit in the SSR register is
set by error detection, clear the PER bit before receiving the parity bit of the next frame.
 During transmission, at least 1 etu is secured as a guard time from the end of the parity bit until the start of the next
frame.
 Since the same data is not retransmitted during transmission, the TEND flag in the SSR register is set 11.5 etu after
transmission start.
 In block transfer mode, the ERS flag in the SSR register indicates the error signal status as in non-block transfer
mode, but the flag is read as 0 because no error signal is transferred.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
(Z)
A Z Z A Z
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(Z)
A Z Z A A
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
23. Serial Communications Interface (SCIg, SCIh)
Z Z A A Z (Z) state
(Z) state
A A A A Z
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