System Clock Control Register 3 (Sckcr3) - Renesas RX100 Series User Manual

RX13T Group
9.2.2

System Clock Control Register 3 (SCKCR3)

Address(es): 0008 0026h
b15 b14
— —
0 0
Value after reset:
Bit Symbol
b7 to b0 —
b10 to b8 CKSEL[2:0]
b15 to b11 —
Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
This register cannot be rewritten while the flash memory is being programmed or erased.
CKSEL[2:0] Bits (Clock Source Select)
These bits select the source of the system clock (ICLK), peripheral module clock (PCLKB, and PCLKD), FlashIF clock
(FCLK), from low-speed on-chip oscillator (LOCO), high-speed on-chip oscillator (HOCO), the main clock oscillator,
and the PLL circuit.
Transitions to clock sources which are not in operation are prohibited.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— — — CKSEL[2:0]
0 0 0 0
Bit Name Description
Reserved These bits are read as 0. The write value should be 0.
Clock Source Select b10 b8
0 0 0: LOCO
0 0 1: HOCO
0 1 0: Main clock oscillator
1 0 0: PLL circuit
Settings other than above are prohibited.
Reserved These bits are read as 0. The write value should be 0.
b9 b8 b7 b6
— —
0 0 0 0
9. Clock Generation Circuit
b5 b4 b3 b2
— — — —
0 0 0 0
Page 133 of 1041
b1 b0
— —
0 0
R/W
R/W
R/W
R/W