Instructions And Pipeline Processing; Instructions Converted Into Single Micro-Operation And Pipeline Processing - Renesas RX100 Series User Manual

RX13T Group
2.8.2

Instructions and Pipeline Processing

The operands in the table below indicate the following meaning.
#IMM: Immediate
flag: bit, flag
Rs, Rs2, Rd, Rd2, Ri, Rb: General-purpose register
CR: Control register
dsp: displacement
pcdsp: displacement
2.8.2.1

Instructions Converted into Single Micro-Operation and Pipeline Processing

The table below lists the instructions that are converted into a single micro-operation. The number of cycles in the table
indicates the number of cycles during no-wait memory access.
Table 2.13 Instructions that are Converted into a Single Micro-Operation
Instruction
Arithmetic/logic instructions
(register-register, immediate-register)
Except EMUL, EMULU, RMPA, DIV,
DIVU and SATR
Arithmetic/logic instructions (division)
Data transfer instructions
(register-register, immediate-register)
Transfer instructions (load operation)
Transfer instructions (store operation)
Bit manipulation instructions (register)
Branch instructions
Floating-point operation instructions
(register-register, immediate-register)
System manipulation instructions
DSP instructions
Note 1. The number of cycles for the dividing instruction varies according to the divisor and dividend.
Note 2. For the number of cycles for throughput and latency, refer to section 2.8.3, Calculation of the Instruction Processing Time.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Mnemonic (indicates the common operation when
the size is omitted)
 {ABS, NEG, NOT} "Rd"/"Rs, Rd"
 {ADC, MAX, MIN, ROTL, ROTR, XOR} "#IMM, Rd"/"Rs,
Rd"
 ADD "#IMM, Rd"/"Rs, Rd"/"#IMM, Rs, Rd"/"Rs, Rs2, Rd"
 {AND, MUL, OR, SUB} "#IMM, Rd"/"Rs, Rd"/"Rs, Rs2, Rd"
 {CMP, TST} "#IMM, Rs"/"Rs, Rs2"
 NOP
 {ROLC, RORC, SAT} "Rd"
 SBB "Rs, Rd"
 {SHAR, SHLL, SHLR} "#IMM, Rd"/"Rs, Rd"/"#IMM, Rs, Rd"
 DIV "#IMM, Rd"/"Rs, Rd"
 DIVU "#IMM, Rd"/"Rs, Rd"
 MOV "#IMM, Rd"/"Rs, Rd"
 {MOVU, REVL, REVW} "Rs, Rd"
 SC Cnd "Rd"
 {STNZ, STZ} "#IMM, Rd"
 {MOV, MOVU} "[Rs], Rd"/"dsp[Rs], Rd"/"[Rs+], Rd"/"[-Rs],
Rd"/"[Ri, Rb], Rd"
 POP "Rd"
 MOV "Rs, [Rd]"/"Rs, dsp[Rd]"/"Rs, [Rd+]"/"Rs, [-Rd]"/"Rs,
[Ri, Rb]"/"#IMM, dsp[Rd]"/"#IMM, [Rd]"
 PUSH "Rs"
 PUSHC "CR"
 SCCnd "[Rd]"/"dsp[Rd]"
 {BCLR, BNOT, BSET} "#IMM, Rd"/"Rs, Rd"
 BM Cnd "#IMM, Rd"
 BTST "#IMM, Rs"/"Rs, Rs2"
 B Cnd "pcdsp"
 {BRA, BSR} "pcdsp"/"Rs"
 {JMP, JSR} "Rs"
 FCMP "#IMM, Rd"/"Rs, Rs2"
 {CLRPSW, SETPSW} "flag"
 MVTC "#IMM, CR"/"Rs, CR"
 MVFC "CR, Rd"
 MVTIPL"#IMM"
 {MACHI, MACLO, MULHI, MULLO} "Rs, Rs2"
 {MVFACHI, MVFACMI} "Rd"
 {MVTACHI, MVTACLO} "Rs"
 RACW"#IMM"
2. CPU
Reference Number of
Figure Cycles
Figure 2.7 1
1
Figure 2.7 3 to 20*
1
Figure 2.7 2 to 18*
Figure 2.7 1
Figure 2.8 Throughput: 1
2
Latency: 2*
Figure 2.9 1
Figure 2.7 1
Figure 2.18 Branch taken: 3
Branch not
taken: 1
Figure 2.7 1
— 1
Figure 2.7 1
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