Renesas V850E/D 3 Series Manuals

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Renesas V850E/D 3 Series User Manual (990 pages)

32-bit Single-Chip Microcontroller

Brand: Renesas | Category: Microcontrollers | Size: 15.75 MB

Table of Contents
6
Chapter 1 Introduction

18
General

18
Features Summary

19
Product Series Overview

23
Description

24
Ordering Information

28
Chapter 2 Pin Functions

29
Overview

29
- Description
  30
- Terms
  34
- Noise Elimination
  34
Port Group Configuration Registers

35
- Overview
  35
- Pin Function Configuration
  36
- Pin Data Input/Output
  41
- Configuration of Electrical Characteristics
  43
- Alternative Input Selection
  46
Port Types Diagrams

51
Port Group Configuration

56
- Port Group Configuration Lists
  57
- Alphabetic Pin Function List
  64
- External Memory Interface of Μpd70F3427
  70
- Port Group 0
  71
- Port Group 1
  73
- Port Group 2
  74
- Port Group 3
  76
- Port Group 4
  78
- Port Group 5
  80
- Port Group 6
  82
- Port Group 7
  84
- Port Group 8
  86
- Port Group 9
  88
- Port Group 10
  90
- Port Group 11
  92
- Port Group 12
  94
- Port Group 13
  95
- Port Group 14 (Μpd70F3427 Only)
  96
Noise Elimination

97
- Analog Filtered Inputs
  97
- Digitally Filtered Inputs
  97
Pin Functions in Reset and Power Save Modes

101
Recommended Connection of Unused Pins

102
Package Pins Assignment

103
- Μpd70F3421, Μpd70F3422, Μpd70F3423
  103
- Μpd70F3424, Μpd70F3425, Μpd70F3426A
  104
- Μpd70F3427
  105
Chapter 3 CPU System Functions

106
Overview

106
- Description
  107
CPU Register Set

108
- General Purpose Registers (R0 to R31)
  109
- System Register Set
  110
Operation Modes

116
- Normal Operation Mode
  116
- Flash Programming Mode
  116
Address Space

117
- CPU Address Space and Physical Address Space
  117
- Program and Data Space
  119
Memory

121
- Memory Areas
  121
- Fixed Peripheral I/O Area
  124
- Recommended Use of Data Address Space
  125
Write Protected Registers

126
Instructions and Data Access Times

128
Chapter 4 Clock Generator

130
Overview

130
- Description
  131
- Clock Monitors
  133
- Power Save Modes Overview
  134
- Start Conditions
  135
- Start-Up Guideline
  136
Clock Generator Registers

137
- General Clock Generator Registers
  139
- SSCG Control Registers
  146
- Control Registers for Peripheral Clocks
  152
- Control Registers for Power Save Modes
  160
- Clock Monitor Registers
  166
Power Save Modes

171
Clock Generator Operation

189
Chapter 5 Interrupt Controller (INTC)

193
Features

193
Non-Maskable Interrupts

202
- Operation
  205
- Restore
  206
- Non-Maskable Interrupt Status Flag (NP)
  207
- NMI0 Control
  207
Maskable Interrupts

208
- Operation
  208
- Restore
  210
- Priorities of Maskable Interrupts
  210
- XXIC - Maskable Interrupts Control Register
  215
- IMR0 to IMR6 - Interrupt Mask Registers
  219
- ISPR - In-Service Priority Register
  222
- Maskable Interrupt Status Flag (ID)
  222
- External Maskable Interrupts
  223
- Software Interrupts
  223
Edge and Level Detection Configuration

224
Software Exception

226
- Operation
  226
- Restore
  227
- Exception Status Flag (EP)
  228
Exception Trap

229
- Illegal Opcode Definition
  229
- Debug Trap
  231
Multiple Interrupt Processing Control

233
Interrupt Response Time

235
Periods in Which Interrupts Are Not Acknowledged

236
Chapter 6 Flash Memory

237
Overview

238
- Flash Memory Address Assignment
  239
- Flash Memory Erasure and Rewrite
  241
- Flash Memory Programming
  242
- Boot Block Swapping
  242
Flash Self-Programming

243
- Flash Self-Programming Registers
  243
- Interrupt Handling During Flash Self-Programming
  245
Flash Programming Via N-Wire

246
Flash Programming with Flash Programmer

247
- Programming Environment
  247
- Communication Mode
  248
- Pin Connection
  251
- Programming Method
  254
Chapter 7 Bus and Memory Control (BCU, MEMC)

258
Overview

258
Description

259
- Memory Banks and Chip Select Signals
  261
- Chips Select Priority Control
  264
- Peripheral I/O Area
  264
- NPB Access Timing
  266
- Bus Properties
  266
- Boundary Operation Conditions
  267
- Initialization for Access to External Devices
  268
- External Bus Mute Function
  268
Registers

269
- BCU Registers
  270
- Memory Controller Registers (Μpd70F3427 Only)
  279
Page ROM Controller

288
Configuration of Memory Access

290
- Endian Format
  290
- Wait Function
  290
- Idle State Insertion
  292
External Devices Interface Timing

292
Page ROM Access Timing

299
- Half Word/Word Access with 8-Bit Bus or Word Access with 16-Bit Bus
  300
- Byte Access with 8-Bit Bus or Byte/Half Word Access with 16-Bit Bus
  302
Data Access Order

304
- Access to 8-Bit Data Busses
  304
- Access to 16-Bit Data Busses
  310
Chapter 8 DMA Controller (DMAC)

316
Features

316
Peripheral and CPU Clock Settings

318
DMAC Registers

320
DMA Setup and Retrigger

332
- DMA Initial Setup (Status after System Reset)
  332
- DMA Retrigger
  332
Automatic Restart Function

333
Transfer Type

334
Transfer Object

334
DMA Channel Priorities

335
DMA Transfer Start Factors

335
Forcible Interruption

336
Forcible Termination

337
DMA Transfer Completion

338
Transfer Mode

339
- Single Transfer Mode
  339
- Block Transfer Mode
  341
Cautions

342
- Simultaneous Program Execution and DMA Transfer with Internal RAM
  342
- MLE Bit Usage
  343
Chapter 9 ROM Correction Function (ROMC)

344
Overview

344
Data Replacement" ROM Correction Unit

345
DBTRAP" ROM Correction Unit

356
- DBTRAP" ROM Correction Operation
  357
- DBTRAP" ROM Correction Registers
  358
Chapter 10 Code Protection and Security

362
Overview

362
Boot ROM

362
N-Wire Debug Interface

362
Flash Writer and Self-Programming Protection

364
Additional Firmware Functions

365
- ID-Field
  365
- Checksum Calculation
  365
- Variable Reset Vector
  365
Chapter 11 16-Bit Timer/Event Counter P (TMP)

366
Overview

366
Functions

367
Configuration

367
TMP Registers

369
Operation

380
Operating Precautions

447
- Capture Operation in Pulse Width Measurement and Free-Running Mode
  447
- Count Jitter for PCLK4 to PCLK7 Count Clocks
  447
Chapter 12 16-Bit Interval Timer Z (TMZ)

448
Overview

448
- Description
  449
- Principle of Operation
  449
TMZ Registers

450
Timing

455
- Steady Operation
  455
- Timer Start and Stop
  456
Features of Timer G

458
Chapter 13 16-Bit Multi-Purpose Timer G (TMG)

458
Function Overview of each Timer Gn

459
Basic Configuration

461
TMG Registers

462
Output Delay Operation

470
Explanation of Basic Operation

471
Operation in Free-Run Mode

473
Match and Clear Mode

483
Edge Noise Elimination

493
Precautions Timer Gn

494
Chapter 14 16-Bit Timer y (TMY)

496
Overview

496
- Description
  497
- Principle of Operation
  498
Registers

498
Timing

503
Output Timing Calculations

504
Chapter 15 Watch Timer (WT)

507
Overview

507
- Description
  509
- Principle of Operation
  510
Watch Timer Registers

512
Watch Timer Operation

516
- Timing of Steady Operation
  516
- Watch Timer Start-Up
  517
Watch Calibration Timer Registers

519
Watch Calibration Timer Operation

525
Chapter 16 Watchdog Timer (WDT)

527
Overview

527
- Description
  527
- Principle of Operation
  528
- Watchdog Timer Clock
  528
- Reset Behavior
  529
Watchdog Timer Registers

530
Chapter 17 Asynchronous Serial Interface (UARTA)

536
Features

536
Configuration

537
UARTA Registers

539
Interrupt Request Signals

546
Operation

547
- Data Format
  547
- SBF Transmission/Reception Format
  549
- SBF Transmission
  551
- SBF Reception
  551
- UART Transmission
  553
- Continuous Transmission Procedure
  554
- UART Reception
  556
- Reception Errors
  557
- Parity Types and Operations
  558
- Receive Data Noise Filter
  559
Baud Rate Generator

560
- Baud Rate Generator Configuration
  560
- Baud Rate Generator Registers
  561
- Baud Rate Calculation
  563
- Baud Rate Error
  563
- Baud Rate Setting Example
  563
- Allowable Baud Rate Range During Reception
  564
- Baud Rate During Continuous Transmission
  566
Cautions

567
Chapter 18 Clocked Serial Interface (CSIB)

569
Features

569
Configuration

570
CSIB Control Registers

571
Operation

580
Output Pins

592
Operation Flow

593
Baud Rate Generator

599
- Overview
  599
- Baud Rate Generator Registers
  599
- Baud Rate Calculation
  601
Cautions

602
- Csibn Behaviour During Debugger Break
  602
- CSIB Operation Stop
  603
Features

605
Chapter 19 I 2 C Bus (IIC)

606
I2C Pin Configuration

606
I2C Pin Configuration

607
I2C Pin Configuration

609
Configuration

611
IIC Registers

614
C Bus Definitions and Control Methods

629
- Start Condition
  630
- Addresses
  631
- Transfer Direction Specification
  632
- Acknowledge Signal (ACK)
  632
- Stop Condition
  634
- Wait Signal (WAIT)
  635
C Bus Pin Functions

629
I 2 C Interrupt Request Signals (Intiicn)

637
Interrupt Request Signal (Intiicn)

655
Address Match Detection Method

656
Error Detection

656
Extension Code

657
Arbitration

658
Wakeup Function

659
Communication Reservation

660
- Communication Reservation Function Is Enabled (Iicfn.iicrsvn Bit = 0)
  660
- Communication Reservation Function Is Disabled (Iicfn.iicrsvn Bit = 1)
  664
Cautions

665
Communication Operations

666
Timing of Data Communication

672
Chapter 20 CAN Controller (CAN)

679
Features

680
- Overview of Functions
  681
- Configuration
  682
CAN Protocol

683
- Frame Format
  683
- Frame Types
  684
- Data Frame and Remote Frame
  684
- Error Frame
  691
- Overload Frame
  692
Functions

693
- Determining Bus Priority
  693
- Bit Stuffing
  693
- Multi Masters
  694
- Multi Cast
  694
- CAN Sleep Mode/Can Stop Mode Function
  694
- Error Control Function
  694
- Baud Rate Control Function
  701
Connection with Target System

704
Internal Registers of CAN Controller

705
- CAN Module Register and Message Buffer Addresses
  705
- CAN Controller Configuration
  706
- CAN Registers Overview
  707
- Register Bit Configuration
  709
Bit Set/Clear Function

712
Control Registers

714
CAN Controller Initialization

750
Message Reception

754
- Receive Data Read
  755
- Receive History List Function
  756
- Mask Function
  758
- Multi Buffer Receive Block Function
  760
- Remote Frame Reception
  761
Message Transmission

762
- Transmit History List Function
  764
- Automatic Block Transmission (ABT)
  766
- Transmission Abort Process
  768
- Remote Frame Transmission
  769
Power Saving Modes

770
- CAN Sleep Mode
  770
- CAN Stop Mode
  773
- Example of Using Power Saving Modes
  774
Interrupt Function

775
Diagnosis Functions and Special Operational Modes

776
- Receive-Only Mode
  776
- Single-Shot Mode
  777
- Self-Test Mode
  778
- Receive/Transmit Operation in each Operation Mode
  779
Time Stamp Function

780
Baud Rate Settings

781
- Baud Rate Setting Conditions
  781
- Representative Examples of Baud Rate Settings
  785
Operation of CAN Controller

789
Chapter 21 A/D Converter (ADC)

818
Functions

818
Configuration

820
ADC Registers

822
Operation

830
- Basic Operation
  830
- Trigger Mode
  831
- Operation Modes
  832
- Power-Fail Compare Mode
  834
Cautions

837
How to Read A/D Converter Characteristics Table

839
Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D)

843
Overview

843
- Driver Overview
  843
Stepper Motor Controller/Driver Registers

846
Operation

851
- Stepper Motor Controller/Driver Operation
  851
Timing

854
- Timer Counter
  854
- Automatic PWM Phase Shift
  855
Chapter 23 LCD Controller/Driver (LCD-C/D)

856
Overview

856
- Description
  857
- LCD Panel Addressing
  858
LCD-C/D Registers

859
Operation

863
- Common Signals and Segment Signals
  863
- Activation of LCD Segments
  865
Display Example

866
Chapter 24 LCD Bus Interface (LCD-I/F)

869
Overview

869
- Description
  870
- LCD Bus Interface Access Modes
  871
- Access Types to the LBDATA0 Register
  871
- Interrupt Generation
  872
LCD Bus Interface Registers

873
Timing

880
- Timing Dependencies
  880
- LCD Bus I/F States During and after Accesses
  881
- Writing to the LCD Bus
  881
- Reading from the LCD Bus
  884
- Write-Read-Write Sequence on the LCD Bus
  886
Cautions

887
- Polling of LBCTL0.TPF0 Flag May Indicate Wrong Status
  887
- Writing to the LBDATA0W/ LBDATA0/ LBDATA0L Register
  887
Chapter 25 Sound Generator (SG)

891
Overview

891
- Description
  892
- Principle of Operation
  893
Sound Generator Registers

895
Sound Generator Operation

901
- Generating the Tone
  901
- Generating the Volume Information
  902
Sound Generator Application Hints

907
- Initialization
  907
- Start and Stop Sound
  907
- Change Sound Volume
  907
- INTSG0 Interrupt
  907
- Constant Sound Volume
  908
- Generate Special Sounds
  908
Chapter 26 Power Supply Scheme

909
Overview

909
Description

911
Voltage Regulators

914
Chapter 27 Reset

915
Overview

915
- General Reset Performance
  916
- Reset at Power-On
  919
- External RESET
  920
- Reset by Watchdog Timer
  921
- Reset by Clock Monitor
  921
- Software Reset
  921
Reset Registers

922
Chapter 28 Voltage Comparator

925
Overview

925
- Description
  926
- Comparison Results
  926
- Stand-By Mode
  926
Voltage Comparator Registers

927
Timing

929
Chapter 29 On-Chip Debug Unit

930
Functional Outline

930
- Debug Functions
  930
- Security Function
  932
Controlling the N-Wire Interface

935
N-Wire Enabling Methods

937
Connection to N-Wire Emulator

939
- KEL Connector
  939
Restrictions and Cautions on On-Chip Debug Function

943
Appendix A Registers Access Times

945
Timer P

946

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Renesas V850E/D 3 Series Manuals

Renesas V850E/D 3 Series User Manual (990 pages)

Table of Contents

Chapter 1 Introduction

General

Features Summary

Product Series Overview

Description

Ordering Information

Chapter 2 Pin Functions

Overview

Port Group Configuration Registers

Port Types Diagrams

Port Group Configuration

Noise Elimination

Pin Functions in Reset and Power Save Modes

Recommended Connection of Unused Pins

Package Pins Assignment

Chapter 3 CPU System Functions

Overview

CPU Register Set

Operation Modes

Address Space

Memory

Write Protected Registers

Instructions and Data Access Times

Chapter 4 Clock Generator

Overview

Clock Generator Registers

Power Save Modes

Clock Generator Operation

Chapter 5 Interrupt Controller (INTC)

Features

Non-Maskable Interrupts

Maskable Interrupts

Edge and Level Detection Configuration

Software Exception

Exception Trap

Multiple Interrupt Processing Control

Interrupt Response Time

Periods in Which Interrupts Are Not Acknowledged

Chapter 6 Flash Memory

Overview

Flash Self-Programming

Flash Programming Via N-Wire

Flash Programming with Flash Programmer

Chapter 7 Bus and Memory Control (BCU, MEMC)

Overview

Description

Registers

Page ROM Controller

Configuration of Memory Access

External Devices Interface Timing

Page ROM Access Timing

Data Access Order

Chapter 8 DMA Controller (DMAC)

Features

Peripheral and CPU Clock Settings

DMAC Registers

DMA Setup and Retrigger

Automatic Restart Function

Transfer Type

Transfer Object

DMA Channel Priorities

DMA Transfer Start Factors

Forcible Interruption

Forcible Termination

DMA Transfer Completion

Transfer Mode

Cautions

Chapter 9 ROM Correction Function (ROMC)

Overview

Data Replacement" ROM Correction Unit

DBTRAP" ROM Correction Unit

Chapter 10 Code Protection and Security

Overview

Boot ROM

N-Wire Debug Interface

Flash Writer and Self-Programming Protection

Additional Firmware Functions