Serial Control Register (Scr) - Renesas RX100 Series User Manual

RX13T Group
23.2.8

Serial Control Register (SCR)

Note: Some bits in the SCR register have different functions in smart card interface mode and non-smart card interface
mode.
(1) Non-Smart Card Interface Mode (SCMR.SMIF = 0)
Address(es): SCI1.SCR 0008 A022h, SCI5.SCR 0008 A0A2h, SCI12.SCR 0008 B302h
b7 b6
TIE RIE
0 0
Value after reset:
Bit Symbol Bit Name
b1, b0 CKE[1:0] Clock Enable
b2 TEIE Transmit End Interrupt Enable
b3 MPIE Multi-Processor Interrupt
Enable
b4 RE Receive Enable
b5 TE Transmit Enable
b6 RIE Receive Interrupt Enable
b7 TIE Transmit Interrupt Enable
x: Don't care
Note 1. Writable only when TE = 0 and RE = 0.
Note 2. 1 can be written only when TE = 0 and RE = 0, while the SMR.CM bit is 1. After setting TE or RE to 1, only 0 can be written to
TE and RE. While the SMR.CM bit is 0 and the SIMR1.IICM bit is 0, writing is enabled under any condition.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
TE RE MPIE TEIE
0 0 0 0
Description
(Asynchronous mode)
b1 b0
0 0: On-chip baud rate generator
0 1: On-chip baud rate generator
1 x: External clock or MTU clock
(Clock synchronous mode)
b1 b0
0 x: Internal clock
1 x: External clock
0: A TEI interrupt request is disabled
1: A TEI interrupt request is enabled
(Valid in asynchronous mode when SMR.MP = 1)
0: Normal reception
1: When the data with the multi-processor bit set to 0 is received,
0: Serial reception is disabled
1: Serial reception is enabled
0: Serial transmission is disabled
1: Serial transmission is enabled
0: RXI and ERI interrupt requests are disabled
1: RXI and ERI interrupt requests are enabled
0: A TXI interrupt request is disabled
1: A TXI interrupt request is enabled
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
CKE[1:0]
0 0
The SCKn pin becomes high-impedance.
The clock with the same frequency as the bit rate is output
from the SCKn pin.
• The clock with a frequency 16 times the bit rate should be
input from the SCKn pin. Input a clock signal with a frequency
eight times the bit rate when the SEMR.ABCS bit is 1.
• The SCKn pin becomes high-impedance when the MTU
clock is used.
The SCKn pin functions as the clock output pin.
The SCKn pin functions as the clock input pin.
the data is not read, and setting the status flags ORER and FER
in SSR to 1 is disabled. When the data with the multi-processor
bit set to 1 is received, the MPIE bit is automatically cleared to 0,
and normal reception is resumed.
R/W
1
R/W*
R/W
R/W
2
R/W*
2
R/W*
R/W
R/W
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