Restrictions On Clock Synchronous Transmission (Clock Synchronous Mode And Simple Spi Mode) - Renesas RX100 Series User Manual

RX13T Group
23.13.6 Restrictions on Clock Synchronous Transmission (Clock Synchronous Mode
and Simple SPI Mode)
When the external clock source is used as a synchronization clock, the following restrictions apply.
(1) Start of transmission
Update TDR by the CPU or DTC and wait for at least five PCLK cycles before allowing the transmit clock to be input
(refer to Figure 23.75 ).
(2) Continuous transmission
(a) Write the next transmit data to TDR or TDRL before the falling edge of the transmit clock (bit 7) (refer to Figure
23.75 ).
(b) When updating TDR after bit 7 has started to transmit, update TDR while the synchronization clock is in the
low-level period, and set the high-level width of the transmit clock (bit 7) to four PCLK cycles or longer (refer to
Figure 23.75 ).
Set t  5 cycles of the PCLK before transmission is started when the external clock is used.
Synchronous clock
(external clock)
TDR
TXI interrupt flag
*1
(ICU.IRn )
Serial transmit data
Set t  4 cycles of the PCLK if TDR is updated after bit 7 is started to transmit when continuous
transmission is performed on the external clock.
Synchronous clock
(external clock)
TDR
TXI interrupt flag
*1
(ICU.IRn )
Serial transmit data
Note 1. Refer to section 14, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.
Figure 23.75 Restrictions on Use of External Clock in Clock Synchronous Transmission
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
t
First frame of data
D0
(1) Start of transmission and (2) Continuous transmission (a)
Previous frame of data
D2
D0 D1 D3
(2) Continuous transmission (b)
23. Serial Communications Interface (SCIg, SCIh)
Update TDR before bit 7 is started to transmit when
continuous transmission is performed on the external clock.
D1 D2 D3 D4
t
Next frame of data
D4 D5 D6 D7
Next frame of data
D5 D6 D7 D0
D0 D1 D2 D3
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D1