Renesas RX100 Series User Manual page 611

RX13T Group
Table 23.18 BRR Settings for Various Bit Rates (Clock Synchronous Mode, Simple SPI Mode)
Bit Rate (bps) n
110
250 3
500 2
1 k 2
2.5 k 1
5 k 1
10 k 0
25 k 0
50 k 0
100 k 0
250 k 0
500 k 0
1 M 0
2 M 0
2.5 M
4 M
5 M
6.25 M
7.5 M
Blank cell: Cannot be set since the bit rate error exceeds 5%.
—: Can be set, but a bit rate error of 1 to 5% will occur.
Note 1. Continuous transmission or reception is not possible. After transmitting/receiving one frame of data, there is an interval of a 1-bit
period before starting transmitting/receiving the next frame of data. The output of the synchronization clock is stopped for a 1-bit
period. For this reason, it takes 9 bits worth of time to transfer one frame (8 bits) of data, and the average transfer rate is 8/9
times the bit rate.
Table 23.19 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode, Simple SPI Mode)
PCLK (MHz) External Input Clock (MHz)
8 1.3333
10 1.6667
12 2.0000
14 2.3333
16 2.6667
18 3.0000
20 3.3333
25 4.1667
30 5.0000
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
8 10
N n N
124 3 155
249 3 77
124 2 155
199 1 249
99 1 124
199 0 249
79 0 99
39 0 49
19 0 24
7 0 9
3 0 4
1
1
0*
1
0 0*
Maximum Bit Rate (Mbps)
1.3333
1.6667
2.0000
2.3333
2.6667
3.0000
3.3333
4.1667
5.0000
23. Serial Communications Interface (SCIg, SCIh)
Operating Frequency PCLK (MHz)
16 20
n N n
3 249
3 124 3
2 249 3
2 99 2
1 199 1
1 99 1
0 159 0
0 79 0
0 39 0
0 15 0
0 7 0
0 3 0
0 1
0
1
0 0*
0
25
N n N
155 3 194
77 3 97
124 2 155
249 2 77
124 1 155
199 0 249
99 0 124
49 0 62
19 0 24
9 — —
4 — —
— —
1
1
0*
1
0 0*
Page 611 of 1041
30
n N
3 233
3 116
2 187
2 93
1 187
1 74
0 149
0 74
0 29
0 14
0 2
1
0 0*