Serial Data Transmission (Asynchronous Mode) - Renesas RX100 Series User Manual

RX13T Group
23.3.7

Serial Data Transmission (Asynchronous Mode)

Figure 23.9 to Figure 23.11 show an example of the operation for serial transmission in asynchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI transfers data from the TDR register *
TXI interrupt handling routine. The TXI interrupt request at the beginning of transmission is generated when the
SCR.TE bit is set to 1 after the SCR.TIE bit is set to 1 or when these 2 bits are set to 1 simultaneously by a single
instruction.
2. Transmission starts after the SPMR.CTSE bit is set to 0 (CTS function is disabled) and a low level on the CTSn#
pin causes data transfer from the TDR register *
interrupt request is generated. Continuous transmission is obtainable by writing the next transmit data to the TDR
1
register * in the TXI interrupt handling routine before transmission of the current transmit data is completed. When
TEI interrupt requests are in use, set the SCR.TIE bit to 0 (a TXI interrupt request is disabled) and the SCR.TEIE bit
to 1 (a TEI interrupt request is enabled) after the last of the data to be transmitted are written to the TDR register *
2
* from the handling routine for TXI requests.
3. Data is sent from the TXDn pin in the following order: start bit, transmit data, parity bit or multi-processor bit (may
be omitted depending on the format), and stop bit.
4. The SCI checks for updating of (writing to) the TDR register *
5. When the TDR register *
input on the CTSn# pin cause the next transfer of the next transmit data from the TDR register *
and sending of the stop bit, after which serial transmission of the next frame starts.
6. If the TDR register *
to put the line in the mark state. If the SCR.TEIE bit is 1 at this time, the SSR.TEND flag is set to 1 and a TEI
interrupt request is generated.
Note 1. Write data not to the TDR register but to the TDRH and TDRL registers when 9-bit data length is selected.
Note 2. Write data in the order from the TDRH register to the TDRL register when 9-bit data length is selected.
Note 3. The SCI checks for updating of the TDRL register only and does not check for updating of the TDRH register
when 9-bit data length is selected.
Figure 23.12 shows a sample flowchart for serial transmission in asynchronous mode.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
3
is updated, setting of the SPMR.CTSE bit to 0 (CTS function is disabled) or a low level
3
is not updated, the SCI sets the SSR.TEND flag to 1, sends the stop bit, and then outputs high
23. Serial Communications Interface (SCIg, SCIh)
1
to the TSR register when data is written to the TDR register *
1
to the TSR register. If the SCR.TIE bit is 1 at this time, a TXI
3
at the time of stop bit output.
1
in the
1 ,
1
to the TSR register
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