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R8C/18 Group, R8C/19 Group
15.1
Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 15.1
lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode
Table 15.1
Clock Synchronous Serial I/O Mode Specifications
Item
Transfer data format
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
Select functions
NOTES:
1. The programming and erasure endurance is defined on a per-block basis. If the programming and
erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1-Kbyte block, and then the block is erased, the erase
count stands at one. When performing 100 or more rewrites, the actual erase count can be reduced
by executing programming operations in such a way that all blank areas are used before performing
an erase operation. Avoid rewriting only particular blocks and try to average out the programming
and erasure endurance of the blocks. It is also advisable to retain data on the erase count of each
block and limit the number of erase operations to a certain number.
2. If an overrun error occurs, the value of the U0RB register will be undefined. The IR bit in the S0RIC
register remains unchanged.
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
• Transfer data length: 8 bits
• CKDIR bit in U0MR register is set to 0 (internal clock): fi/(2(n+1)).
fi = f1, f8, f32 n = value set in U0BRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): input from CLK0 pin.
• Before transmission starts, the following requirements must be met.
- The TE bit in the U0C1 register is set to 1 (transmission enabled).
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register).
• Before reception starts, the following requirements must be met.
- The RE bit in the U0C1 register is set to 1 (reception enabled).
- The TE bit in the U0C1 register is set to 1 (transmission enabled).
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register).
• When transmitting, one of the following conditions can be selected.
- The U0IRS bit is set to 0 (transmit buffer empty):
When transferring data from the U0TB register to UART0 transmit
register (when transmission starts).
- The U0IRS bit is set to 1 (transmission completes):
When completing data transmission from UARTi transmit register.
• When receiving
When data transfer from the UART0 receive register to the U0RB register
(when reception completes).
(2)
• Overrun error
This error occurs if the serial interface starts receiving the next data item
before reading the U0RB register and receives the 7th bit of the next data.
• CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
• LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
• Continuous receive mode selection.
Receive is enabled immediately by reading the U0RB register.
Page 152 of 233
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Specification
15. Serial Interface
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