Renesas RX100 Series User Manual page 730

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RS Bit (Restart Condition Issuance Request)

This bit is used to request that a restart condition be issued in master mode.

When this bit is set to 1 to request to issue a restart condition, a restart condition is issued when the BBSY flag is set to 1

(bus busy state) and the MST bit is set to 1 (master mode).

For details on the restart condition issuance, refer to section 24.10, Start Condition/Restart Condition/Stop

Condition Issuing Function .

[Setting condition]

 When 1 is written to the RS bit with the ICCR2.BBSY flag set to 1

[Clearing conditions]

 When 0 is written to the RS bit

 When a restart condition has been issued (a start condition is detected)

 When the ICSR2.AL (arbitration-lost) flag is set to 1

 When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset

Do not set the RS bit to 1 while issuing a stop condition.

If 1 (requests to issue a restart condition) is written to the RS bit in slave mode, the restart condition is not issued

but the RS bit remains set to 1. If the operating mode changes to master mode with the bit not being cleared, note

that the restart condition may be issued.

SP Bit (Stop Condition Issuance Request)

This bit is used to request that a stop condition be issued in master mode.

When this bit is set to 1 to request to issue a stop condition, a stop condition is issued when the BBSY flag is set to 1 (bus

busy state) and the MST bit is set to 1 (master mode).

For details on the stop condition issuance, refer to section 24.10, Start Condition/Restart Condition/Stop Condition

Issuing Function .

[Setting condition]

 When 1 is written to the SP bit with both the BBSY flag and the ICCR2.MST bit set to 1

[Clearing conditions]

 When 0 is written to the SP bit

 When a stop condition has been issued (a stop condition is detected)

 When the ICSR2.AL (arbitration-lost) flag is set to 1

 When a start condition and a restart condition are detected

 When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset

Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).

Do not set the SP bit to 1 while a restart condition is being issued.

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

C-bus Interface (RIICa)

Page 730 of 1041