Cac Control Register 2 (Cacr2) - Renesas RX100 Series User Manual

RX13T Group
10.2.3

CAC Control Register 2 (CACR2)

Address(es): 0008 B002h
b7 b6
DFS[1:0]
Value after reset: 0 0
Bit Symbol
b0 RPS
b3 to b1 RSCS[2:0]
b5, b4 RCDS[1:0]
b7, b6 DFS[1:0]
Note: Set the CACR2 register when the CACR0.CFME bit is 0.
RPS Bit (Reference Signal Select)
This bit selects whether to use the CACREF pin input or an internal clock (internally generated signal) as the reference
signal.
RSCS[2:0]Bits (Measurement Reference Clock Select)
These bits select the clock source for generating the measurement reference clock.
RCDS[1:0]Bits (Measurement Reference Clock Frequency Division Ration Select)
These bits select the frequency division ratio of the measurement reference clock.
DFS[1:0]Bits (Digital Filter Select)
The setting of these bits enables or disables the digital filter and selects its sampling clock.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
RCDS[1:0] RSCS[2:0]
0 0 0 0
Bit Name
Reference Signal Select
Measurement Reference Clock
Select
Measurement Reference Clock
Frequency Division Ration Select
Digital Filter Select
10. Clock Frequency Accuracy Measurement Circuit (CAC)
b1 b0
RPS
0 0
Description
0: CACREF pin input
1: Internal clock (internally generated signal)
b3 b1
0 0 0: Main clock
0 1 0: HOCO clock
0 1 1: LOCO clock
1 0 0: IWDT-dedicated clock (IWDTCLK)
1 0 1: Peripheral module clock B (PCLKB)
Settings other than above are prohibited.
b5 b4
0 0: ×1/32 clock
0 1: ×1/128 clock
1 0: ×1/1024 clock
1 1: ×1/8192 clock
b7 b6
0 0: Digital filtering is disabled.
0 1: The sampling clock for the digital filter is the
measurement target clock.
1 0: The sampling clock for the digital filter is the
measurement target clock divided by 4.
1 1: The sampling clock for the digital filter is the
measurement target clock divided by 16.
R/W
R/W
R/W
R/W
R/W
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