Smart Card Mode Register (Scmr) - Renesas RX100 Series User Manual

RX13T Group
23.2.10

Smart Card Mode Register (SCMR)

Address(es): SCI1.SCMR 0008 A026h, SCI5.SCMR 0008 A0A6h, SCI12.SCMR 0008 B306h,
SMCI1.SCMR 0008 A026h, SMCI5.SCMR 0008 A0A6h, SMCI12.SCMR 0008 B306h
b7 b6
BCP2 —
1 1
Value after reset:
Bit Symbol Bit Name
b0 SMIF Smart Card Interface Mode
Select
b1 — Reserved
b2 SINV Transmitted/Received Data
Invert
b3 SDIR Transmitted/Received Data
Transfer Direction
b4 CHR1 Character Length 1
b6, b5 — Reserved
b7 BCP2 Base Clock Pulse 2
Note 1. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
Note 2. The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.
Note 3. LSB first should be selected and the value of MSB (b7) in the TDR register cannot be transmitted.
SMIF Bit (Smart Card Interface Mode Select)
When this bit is set to 1, smart card interface mode is selected.
When this bit is set to 0, non-smart card interface mode, i.e., asynchronous mode (including multi-processor mode),
clock synchronous mode, simple SPI mode, or simple I
SINV Bit (Transmitted/Received Data Invert)
Inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit. To invert the parity
bit, invert the PM bit in the SMR register.
CHR1 Bit (Character Length 1)
Selects the data length of transmit/receive data.
Selects in combination with the CHR bit in SMR.
A fixed data length of 8 bits is used in modes other than asynchronous mode.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— CHR1 SDIR SINV
1 1 0 0
Description
0: Non-smart card interface mode
(Asynchronous mode, clock synchronous mode, simple SPI mode,
or simple I
1: Smart card interface mode
This bit is read as 1. The write value should be 1.
0: TDR contents are transmitted as they are. Receive data is stored as
it is in RDR.
1: TDR contents are inverted before being transmitted. Receive data is
stored in inverted form in RDR.
This bit can be used in the following modes.
 Smart card interface mode
 Asynchronous mode (multi-processor mode)
 Clock synchronous mode
 Simple SPI mode
Set this bit to 1 if operation is to be in simple I
0: Transfer with LSB first
1: Transfer with MSB first
(Only valid in asynchronous mode)*
Selects in combination with the SMR.CHR bit.
CHR1 CHR
0
0
1
1
These bits are read as 1. The write value should be 1.
Selects the number of base clock cycles in combination with the
SMR.BCP[1:0] bits.
Table 23.9 lists the combinations of the SCMR.BCP2 bit and
SMR.BCP[1:0] bits.
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
— SMIF
1 0
2
C mode)
0: Transmit/receive in 9-bit data length
1: Transmit/receive in 9-bit data length
0: Transmit/receive in 8-bit data length (initial value)
1: Transmit/receive in 7-bit data length*
2
C mode is selected.
2
C mode.
2
3
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R/W
1
R/W*
R/W
1
R/W*
1
R/W*
1
R/W*
R/W
1
R/W*