Pll Control Register (Pllcr) - Renesas RX100 Series User Manual

RX13T Group
9.2.3

PLL Control Register (PLLCR)

Address(es): 0008 0028h
b15 b14
— —
0 0
Value after reset:
Bit Symbol
b1, b0 PLIDIV[1:0]
b7 to b2 —
b13 to b8 STC[5:0]
b15, b14 —
Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
Writing to the PLLCR is prohibited when the PLLCR2.PLLEN bit is 0 (PLL is operating).
PLIDIV[1:0] Bits (PLL Input Frequency Division Ratio Select)
These bits select the frequency division ratio of the PLL clock source.
Set these bits so that the frequency of PLL input signal is within the range of 4 MHz to 8 MHz.
STC[5:0] Bits (Frequency Multiplication Factor Select)
These bits select the frequency multiplication factor of the PLL circuit.
Set these bits so that the PLL oscillation frequency is within the range of 24 MHz to 32 MHz.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
STC[5:0]
0 0 1 1
Bit Name Description
PLL Input Frequency
b1 b0
0 0: ×1
Division Ratio Select
0 1: ×1/2
1 0: ×1/4
1 1: Setting prohibited
Reserved These bits are read as 0. The write value should be 0.
Frequency Multiplication
b13
0 0 0 1 1 1: ×4
Factor Select
0 0 1 0 0 0: ×4.5
0 0 1 0 0 1: ×5
0 0 1 0 1 0: ×5.5
0 0 1 0 1 1: ×6
0 0 1 1 0 0: ×6.5
0 0 1 1 0 1: ×7
0 0 1 1 1 0: ×7.5
0 0 1 1 1 1: ×8
Settings other than above are prohibited.
Reserved These bits are read as 0. The write value should be 0.
b9 b8 b7 b6
— —
1 1 0 0
b8
9. Clock Generation Circuit
b5 b4 b3 b2
— — — —
0 0 0 0
Page 134 of 1041
b1 b0
PLIDIV[1:0]
0 0
R/W
R/W
R/W
R/W
R/W