Interrupt Source - Renesas RX100 Series User Manual

RX13T Group
(5) SCI Setting
Set the SCIk.SCR.RIE bit to 1 to enable the RXI interrupt. If a reception error occurs during the SCI receive operation,
subsequent receptions are not performed. Accordingly, make settings so that the CPU can accept receive error interrupts.
(6) Start of the Sequence Transfer
On completion of reception of 1-byte data by the SCI, an RXI interrupt is generated to start the DTC. The DTC transfers
the received data from the SCIk.RDR register to the RAM. The DTC looks up the DTC index table by using the value
from the received data (sequence number) and continues to transfer data corresponding to the that number.
When the CPUSEL bit in the DTC index is 1, the DTC does not read the transfer information and sets the
ICU.DTCERn.DTCE bit to 0. Then the DTC outputs an interrupt request to the CPU and ends the sequence transfer.
(7) During Suspension of the Sequence Transfer
Set the ICU.DTCERn.DTCE bit to 1 if the bit is 0. The DTC continues to transfer the data for every generation of the
DTC transfer request in response to the corresponding RXI interrupt.
(8) End of the Sequence Transfer
Set the MRB.SQEND bit in the last transfer information of the sequence transfer to 1. After execution of this data
transfer, the DTC ends the sequence transfer. The DTC starts to refer to the DTC vector table when a DTC transfer
request is generated due to the next corresponding RXI interrupt.
16.7

Interrupt Source

When the DTC has finished data transfer of specified count or when data transfer with the MRB.DISEL bit set to 1 (an
interrupt request to the CPU is generated each time the data transfer is performed) has been completed, an interrupt to the
CPU is generated by the DTC trigger source. Such interrupts to the CPU are controlled according to the PSW.I bit
(interrupt enable) of the CPU, the PSW.IPL[3:0] bits (processor interrupt priority level), and the priority level of the
interrupt controller.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
16. Data Transfer Controller (DTCb)
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