Serial Communications Interface (Scig, Scih); Overview - Renesas RX100 Series User Manual

RX13T Group
23.

Serial Communications Interface (SCIg, SCIh)

This MCU has three independent serial communications interface (SCI) channels. The SCI consists of the SCIg module
(SCI1 and SCI5) and the SCIh module (SCI12).
The SCIg module (SCI1 and SCI5) can handle both asynchronous and clock synchronous serial communications.
Asynchronous serial data communications can be carried out with standard asynchronous communications chips such as
a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communications Interface Adapter (ACIA).
As an extended function in asynchronous communications mode, the SCI also supports smart card (IC card) interfaces
conforming to ISO/IEC 7816-3 (standard for Identification Cards). The SCI is also supports simple SPI interfaces, and
2
simple I C-bus interfaces when configured for single-master systems.
The SCIh module includes the functions of the SCIg module, and supports an extended serial communication protocol
formed of Start Frames and Information Frames.
In this section, "PCLK" is used to refer to PCLKB.
23.1

Overview

Table 23.1 lists the specifications of the SCIg module, Table 23.2 lists the specifications of the SCIh module, and
Table 23.3 lists the specifications of the individual SCI channels.
Figure 23.1 shows the block diagram of SCI1 and SCI5 and Figure 23.2 shows the block diagram of SCI12 (SCIh).
Table 23.1 SCIg Specifications (1/2)
Item
Serial communication modes
Transfer speed
Full-duplex communications
I/O pins
Data transfer
Interrupt sources
Low power consumption function
Asynchronous mode Data length
Transmission stop bit
Parity
Receive error detection
Hardware flow control
Start-bit detection
Break detection
Clock source
Double-speed mode
Multi-processor
communications function
Noise cancellation
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
23. Serial Communications Interface (SCIg, SCIh)
Description
 Asynchronous
 Clock synchronous
 Smart card interface
 Simple I
2 C-bus
 Simple SPI bus
Bit rate specifiable with the on-chip baud rate generator.
Transmitter: Continuous transmission possible using double-buffer structure.
Receiver: Continuous reception possible using double-buffer structure.
Refer to Table 23.4 to Table 23.6.
Selectable as LSB first or MSB first transfer*
Transmit end, transmit data empty, receive data full, and receive error
Completion of generation of a start condition, restart condition, or stop condition (for
simple I 2 C mode)
Module stop state can be set for each channel.
7, 8, or 9 bits
1 or 2 bits
Even parity, odd parity, or no parity
Parity, overrun, and framing errors
CTSn# and RTSn# pins can be used in controlling transmission/reception.
Low level or falling edge is selectable.
When a framing error occurs, a break can be detected by reading the RXDn pin
level directly.
An internal or external clock can be selected.
Transfer rate clock input from the MTU can be used. (SCI1, SCI5)
Baud rate generator double-speed mode is selectable.
Serial communication among multiple processors
The signal paths from input on the RXDn pins incorporate digital noise filters.
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