Renesas RX100 Series User Manual page 616

RX13T Group
ACS0 Bit (Asynchronous Mode Clock Source Select)
Selects the clock source in the asynchronous mode.
The ACS0 bit is valid in asynchronous mode (SMR.CM bit = 0) and when an external clock input is selected
(SCR.CKE[1:0] bits = 10b or 11b). This bit is used to select an external clock input or the logical AND of compare
matches output from the internal MTU.
Set the ACS0 bit to 0 in other than asynchronous mode.
The MTIOC1A and MTIOC2A output of the MTU can be set as the base clock source. Refer to Table 23.25 for details.
Table 23.25 Correspondence between SCI Channels and Compare Match Outputs
SCI MTU
SCI1 MTU1, MTU2
SCI5 MTU1, MTU2
SCI12 MTU1, MTU2
Figure 23.3 shows a setting example of when MTIOC1A and MTIOC2A in the MTU are selected for output.
This figure shows an example when MTU clock is input to SCIn (n = 1, 5, 12).
When generating 187.5 kbps of MTU average transfer rate for PCLK = 32 MHz:
(1) Generate a frequency of 4 MHz using MTIOC1A as the clock source.
(2) Set MTIOC2A to the PWM output of 1 MHz and generate 3/4 clock enable to set an average
transfer rate of 3 MHz/16 = 187.5 kbps.
Setting examples of MTU and SCI
• MTU1.TCR = 20h, MTU2.TCR = 20h (TCNT is cleared at compare match in TGRA,
the count is incremented at rising edge of PCLK/1)
• MTU1.TMDR1 = 02h, MTU2.TMDR1 = 02h (Operating mode is set to PWM mode 1)
• MTU1.TIORH = 12h, MTU2.TIORH = 12h (High is output at compare match in TGRA,
Low is output at compare match in TGRB)
• MTU1.TCNT = MTU7.TCNT = 0000h
• MTU1.TGRA = 07h, MTU1.TGRB = 03h
• MTU2.TGRA = 1Fh, MTU2.TGRB = 17h
• SCIn.SCR.SCK[1:0] = 10b (External clock input or MTU clock input is selected)
• SCIn.SEMR = 01h (MTU clock input is selected)
Clock source
1 2
MTIOC1A output
4 MHz
Clock enable
MTIOC2A output
1 2
SCKn base clock
= 4 MHz × 3/4
= 3 MHz (average)
3 MHz
1 2
1 bit = Base clock × 16
Average transfer rate = 3 MHz/16 = 187.5 kbps
Figure 23.3 Example of Average Transfer Rate Setting When MTU Clock is Input
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Compare Match Output
MTIOC1A, MTIOC2A
MTIOC1A, MTIOC2A
MTIOC1A, MTIOC2A
3 4 1 2 3 4 1 2
3 1 2 3 1 2
4 MHz
3 4 5 6 7 8
23. Serial Communications Interface (SCIg, SCIh)
MTU1, MTU2
MTIOC1A
MTIOC2A
3 4 4
1 2 3 1 2
3
1 2 3 1 2
9 10 11 12 13 14
SCI1
Clock source
Clock enable
SCI5
SCI12
4 1 2 3 4 1 2
3
1 2 3 1 2
3
15 16 1 2 3 4
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SCK1
SCK5
SCK12
3 4
3
5