Slave Receive Operation - Renesas RX100 Series User Manual

RX13T Group
24.3.6

Slave Receive Operation

In slave receive operation, the master device outputs the SCL clock and transmit data, and the RIIC returns
acknowledgments as a slave device.
Figure 24.18 shows an example of usage of slave reception and Figure 24.19 and Figure 24.20 show the timing of
operations in slave reception.
The following describes the procedure and operations for slave reception.
(1) Initial settings. For details, refer to section 24.3.2, Initial Settings .
After initial settings, the RIIC will stay in the standby state until it receives a slave address that it matches.
(2) After receiving a matching slave address, the RIIC sets one of the corresponding bits ICSR1.HOA, GCA, and AASy
(y = 0 to 2) to 1 on the rising edge of the ninth cycle of SCL clock (the clock signal) and outputs the value set in the
ICMR3.ACKBT bit to the acknowledge bit on the ninth cycle of SCL clock. If the value of the R/W# bit that was
also received at this time is 0, the RIIC continues to place itself in slave receive mode and sets the ICSR2.RDRF
flag to 1.
(3) After the ICSR2.STOP flag is confirmed to be 0 and the ICSR2.RDRF flag to be 1, dummy read the ICDRR register
(the dummy value consists of the slave address and R/W# bit when the 7-bit address format is selected, or the lower
8 bits when the 10-bit address format is selected).
(4) When the ICDRR register is read, the RIIC automatically sets the ICSR2.RDRF flag to 0. If reading of the ICDRR
register is delayed and a next byte is received while the RDRF flag is still set to 1, the RIIC holds the SCL0 line low
from one SCL cycle before the timing with which RDRF should be set. In this case, reading the ICDRR register
releases the SCL0 line from being held at the low level.
When the ICSR2.STOP flag is 1 and the ICSR2.RDRF flag is also 1, read the ICDRR register until all the data is
completely received.
(5) Upon detecting the stop condition, the RIIC automatically clears bits ICSR1.HOA, GCA, and AASy (y = 0 to 2) to
0.
(6) After checking that the ICSR2.STOP flag is 1, set the ICSR2.STOP flag to 0 for the next transfer operation.
Slave reception
ICSR2.STOP = 0?
No
ICSR2.RDRF = 1?
Read ICDRR register
No
All data received?
No
ICSR2.STOP = 1?
ICSR2.STOP = 0
End of slave reception
Figure 24.18 Example of Slave Reception Flowchart
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Initial settings
No
Yes
Yes
Yes
Yes
Yes
No
ICSR2.RDRF = 1?
Yes
Read ICDRR register
(last data)
2
24. I C-bus Interface (RIICa)
[1] Initial settings
[2], [3], [4] Read receive data
(Dummy read first)
[5] Check stop condition detection
[6] Processing for the next transfer
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