24.13 Interrupt Sources; Buffer Operation For Txi And Rxi Interrupts - Renesas RX100 Series User Manual

RX13T Group

24.13 Interrupt Sources

The RIIC issues four types of interrupt request: transfer error or event generation (arbitration-lost, NACK detection,
timeout detection, start condition detection, and stop condition detection), receive data full, transmit data empty, and
transmit end.
Table 24.6 lists details of the several interrupt requests. The receive data full and transmit data empty are both capable of
activating data transfer by the DTC.
Table 24.6 Interrupt Sources
Symbol Interrupt Source
EEI Transfer error/
event generation
2
RXI* Receive data full
1
TXI* Transmit data empty
3
TEI* Transmit end
Note: There is a delay time between the execution of a write instruction for a peripheral module by the CPU and actual writing to the
module. Thus, when an interrupt flag has been cleared or an interrupt request has been masked, read the relevant flag again to
check whether clearing or masking has been completed, and then return from interrupt handling. Returning from interrupt
handling without checking that writing to the module has been completed creates a possibility of repeated processing of the
same interrupt.
Note 1. Because TXI is an edge-detected interrupted, it does not require clearing. Furthermore, the ICSR2.TDRE flag (a condition for
TXI) is automatically set to 0 when data for transmission are written to the ICDRT register or a stop condition is detected
(ICSR2.STOP flag is 1).
Note 2. Because RXI is an edge-detected interrupted, it does not require clearing. Furthermore, the ICSR2.RDRF flag (a condition for
RXI) is automatically set to 0 when data are read from the ICDRR register.
Note 3. When using the TEI interrupt, clear the ICSR2.TEND flag in the TEI interrupt handling.
Note that the ICSR2.TEND flag is automatically set to 0 when data for transmission are written to the ICDRT register or a stop
condition is detected (ICSR2.STOP flag is 1).
Clear the each flag or mask the interrupt request during interrupt handling.
24.13.1

Buffer Operation for TXI and RXI Interrupts

If the conditions for generating a TXI and RXI interrupt are satisfied while the corresponding IR flag is 1, the interrupt
request is not output for the ICU but retained internally (the capacity for internal retention is one request per source).
An interrupt request that was being retained internally is output to the ICU when the value of the ICU.IRn.IR flag
becomes 0. Internally retained interrupt requests are automatically cleared under normal conditions of usage.
Internally retained interrupt requests can also be cleared by writing 0 to the corresponding interrupt enable bit in the
ICIER register.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Interrupt Flag DTC Activation
AL Not possible
NACKF
TMOF
START
STOP
RDRF Possible
TDRE Possible
TEND Not possible
2
24. I C-bus Interface (RIICa)
Interrupt Condition
AL = 1 and ALIE = 1
NACKF = 1 and NAKIE = 1
TMOF = 1 and TMOIE = 1
START = 1 and STIE = 1
STOP = 1 and SPIE = 1
RDRF = 1 and RIE = 1
TDRE = 1 and TIE = 1
TEND = 1 and TEIE = 1
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