Pipeline Basic Operation - Renesas RX100 Series User Manual

RX13T Group
2.8.2.3

Pipeline Basic Operation

In the ideal pipeline processing, each stage is executed in one cycle, though all instructions may not be pipelined in due
to the processing in each stage and the branch execution.
The CPU controls the pipeline stage with the IF stage in the unit of instructions, while the D and subsequent stages in the
unit of micro-operations.
The figures below show the pipeline processing of typical cases.
Note: mop: Micro-operation, stall: Pipeline stall
(1) Pipeline Flow with Stalls
DIV R1, R2
ADD R3, R4
ADD R5, R6
Figure 2.16 When an Instruction which Requires Multiple Cycles is Executed in the E Stage
MOV [R1], R2
MOV [R3], R4
ADD R5, R6
Figure 2.17 When an Instruction which Requires more than One Cycle for its Operand Access is Executed
Figure 2.18 When a Branch Instruction is Executed (an Unconditional Branch Instruction is Executed or
the Condition is Satisfied for a Conditional Branch Instruction)
MOV [R2], R1
ADD R2, R1
Figure 2.19 When the Subsequent Instruction Uses an Operand Read from the Memory
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
IF D E E
IF D stall
IF stall
IF D E M
IF D E
IF D
Branch instruction is executed
Branch
IF D
instruction
IF D
IF
E WB
stall E
stall D
Other than no-wait
memory access
M
M
stall stall
stall stall
E
Branch penalty
2 cycles
IF D E
E M WB
Bypass process
D stall E WB
(mop) div
(mop) add
WB
(mop) add
E WB
(mop) load
WB
(mop) load
M WB
(mop) add
E WB
(mop) jump
WB
(mop) load
(mop) add
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2. CPU