Write Buffer Function (Internal Peripheral Bus) - Renesas RX100 Series User Manual

RX13T Group
15.2.5

Write Buffer Function (Internal Peripheral Bus)

The internal peripheral bus has the write buffer function, which allows the next round of bus access to start, before the
current write access is completed, in write access. However, if the following round of bus access is from the same bus
master but to the different internal peripheral bus, it is suspended until the bus operations already in progress are
completed. When read access to the internal memory is scheduled after the write access to the internal peripheral bus
from the CPU, the following round of bus access can be started before the current bus operation is completed and thus
the order of accesses may be changed (see Figure 15.3 ).
Access by the CPU:
(1) Peripheral bus 1 (W)  (2) Peripheral bus 1 (W)  (3) Peripheral bus 2 (W)  (4) Peripheral bus 2 (W) 
(5) RAM (R)  (6) RAM (R)
Number of access cycles: 1 cycle (peripheral bus 1), 2 cycles (peripheral bus 2)
Internal peripheral bus 1
Internal peripheral bus 2
Memory bus 1
Figure 15.3 Write Buffer Function
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Write access to peripheral bus 1
Peripheral Peripheral
bus 1 bus 1
(1) (2)
Write access to peripheral bus 2
Peripheral bus 2 Peripheral bus 2
(3)
Read access to RAM
RAM
(5)
15. Buses
(4)
RAM
(6)
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