Sci Initialization (Simple Spi Mode); Transmission And Reception Of Serial Data (Simple Spi Mode); Bit Rate Modulation Function - Renesas RX100 Series User Manual

RX13T Group
23.8.5

SCI Initialization (Simple SPI Mode)

The procedure is the same as for initialization in clock synchronous mode Figure 23.23 , Sample SCI Initialization
Flowchart. The CKPOL and CKPH bits in the SPMR must be set to ensure that the kind of clock signal they select is
suitable for both master and slave devices.
For initialization, changes to the operating mode, changes to the transfer format, and so on, initialize the SCR register
before proceeding with changes.
As well as setting the RE bit to 0, note that the SSR.ORER, FER, and PER flags, as well as the RDR, are not initialized.
Note that changing the value of the TE bit from 1 to 0 or from 0 to 1 will lead to the generation of a transmit data empty
interrupt (TXI) if the value of the TIE bit in the SCR is 1 at the time.
23.8.6

Transmission and Reception of Serial Data (Simple SPI Mode)

In master operation, ensure that the SSn# pin of the slave device on the other side of the transfer is at the low level before
starting the transfer and at the high level on completion of the transfer. Otherwise, the procedures are the same as in clock
synchronous mode.
23.9

Bit Rate Modulation Function

The bit rate modulation function corrects the bit rate by thinning out the specified amount of clocks from those input to
the baud rate generator.
When the SEMR.BRME bit is 1, the baud rate generator validates and counts the average interval of the number of
clocks set in the MDDR register out of the total 256 clocks input.
Figure 23.58 assumes the SCI is in asynchronous mode, bits SMR.CKS[1:0] are 00b, the BRR register is 00h, and the
MDDR register is 160. In this example, the cycle of the base clock is evenly corrected to 256/160, and the bit rate is
corrected to 160/256. Note that there is an imbalance in thinning out the internal clock, and expansion and contraction
occur in the pulse width of the base clock.
Note: Do not use this function in clock synchronous mode and in the highest speed settings in simple SPI mode
(SMR.CKS[1:0] = 00b, SCR.CKE[1] = 0, and BRR = 0).
(1) Example when not using bit rate modulation
Internal clock
(bit rate counter input)
Base clock
Transmit data/receive data
(2) Example when using bit rate modulation, and corrected to
96 out of 256 clocks are disabled by the MDDR register setting (160 clocks are enabled)
Internal clock
(bit rate counter input)
1 2
Base clock
Transmit data/receive data
Figure 23.58 Example of the Base Clock When the Bit Rate Modulation Function is Used
The input of a clock signal with a shorter period to the baud rate generator reduces difference in the generated base clock
period and, since the division ratio of the baud rate generator also becomes larger, reduces difference in the length of the
1-bit period.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
1-bit period is 16 cycles of the base clock
160
256
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2
1 2 3 4 5 6 7 8 9 10
23. Serial Communications Interface (SCIg, SCIh)
11 12 13 14 15 16 17 18 19 20
1-bit period is 16 cycles of the base clock
52
This bit extends the 1-bit period to (average 1-bit period is corrected to
32
21 22 23 24 25 26 27 28 29 30
256
)
160
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