I 2 C-Bus Interface (Riica); Overview - Renesas RX100 Series User Manual

RX13T Group
2
24. I C-bus Interface (RIICa)
This MCU has a single-channel I
The RIIC module conforms with the NXP I
In this section, "PCLK" is used to refer to PCLKB.
24.1

Overview

Table 24.1 lists the specifications of the RIIC, Figure 24.1 shows a block diagram of the RIIC, and Figure 24.2 shows
an example of I/O pin connections to external circuits (I
the RIIC.
Table 24.1 RIIC Specifications (1/2)
Item
Communications format
Transfer rate
SCL clock
Issuing and detecting
conditions
Slave address
Acknowledgment
Wait function
SDA output delay
function
Arbitration
Timeout function
Noise cancellation
Interrupt sources
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
2
C-bus interface (RIIC).
2
C-bus (Inter-IC bus) interface and provides a subset of its functions.
Description
 I
2
C-bus format or SMBus format
 Master mode or slave mode selectable
 Automatic securing of the various setup times, hold times, and bus-free times for the transfer rate
Fast-mode is supported (up to 400 kbps)
For master operation, the duty cycle of the SCL clock is selectable in the range from 4 to 96%.
Start, restart, and stop conditions are automatically generated. Start conditions (including restart conditions)
and stop conditions are detectable.
 Up to three different slave addresses can be set.
 7-bit and 10-bit address formats are supported (along with the use of both at once).
 General call addresses, device ID addresses, and SMBus host addresses are detectable.
 For transmission, the acknowledge bit is automatically loaded.
Transfer of the next data for transmission can be automatically aborted on detection of a
not-acknowledge bit.
 For reception, the acknowledge bit is automatically transmitted.
If a wait between the eighth and ninth clock cycles has been selected, software control of the value in the
acknowledge field in response to the received value is possible.
 In reception, the following periods of waiting can be obtained by holding the SCL clock at the low level:
Waiting between the eighth and ninth clock cycles
Waiting between the ninth clock cycle and the first clock cycle of the next transfer
Timing of the output of transmitted data, including the acknowledge bit, can be delayed.
 For multi-master operation
Operation to synchronize the SCL clock in cases of conflict with the SCL signal from another master is
possible.
When issuing the start condition would create conflict on the bus, loss of arbitration is detected by testing
for non-matching between the internal signal for the SDA line and the level on the SDA line.
In master operation, loss of arbitration is detected by testing for non-matching between the signal on the
SDA line and the internal signal for the SDA line.
 Loss of arbitration due to detection of the start condition while the bus is busy is detectable (to prevent the
issuing of double start conditions).
 Loss of arbitration in transfer of a not-acknowledge bit due to the internal signal for the SDA line and the
level on the SDA line not matching is detectable.
 Loss of arbitration due to non-matching of internal and line levels for data is detectable in slave
transmission.
The internal timeout function is capable of detecting long-interval stop of the SCL clock.
The interface incorporates digital noise filters for both the SCL and SDA signals, and the width for noise
cancellation by the filters is adjustable by software.
Four sources:
 Error in transfer or occurrence of events
Detection of arbitration, NACK, timeout, a start condition including a restart condition, or a stop condition
 Receive data full (including matching with a slave address)
 Transmit data empty (including matching with a slave address)
 Transmit end
2
C-bus configuration example). Table 24.2 lists the I/O pins of
2
24. I C-bus Interface (RIICa)
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