Nmi Pin Interrupt Control Register (Nmicr); Nmi Pin Digital Filter Enable Register (Nmiflte) - Renesas RX100 Series User Manual

RX13T Group
14.2.13

NMI Pin Interrupt Control Register (NMICR)

Address(es): ICU.NMICR 0008 7583h
b7 b6
— —
Value after reset: 0 0
Bit Symbol Bit Name
b2 to b0 — Reserved
b3 NMIMD NMI Detection Set
b7 to b4 — Reserved
Change the setting of the NMICR register before the NMI pin interrupt is enabled (before setting the NMIER.NMIEN bit
to 1).
NMIMD Bit (NMI Detection Set)
This bit specifies the detection edge of the NMI pin interrupt.
14.2.14

NMI Pin Digital Filter Enable Register (NMIFLTE)

Address(es): ICU.NMIFLTE 0008 7590h
b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 NFLTEN NMI Digital Filter Enable
b7 to b1 — Reserved
NFLTEN Bit (NMI Digital Filter Enable)
This bit enables the digital filter used for the NMI pin interrupt.
The digital filter is enabled when the NFLTEN bit is 1, and disabled when the NFLTEN bit is 0.
The NMI pin level is sampled at the sampling clock cycle specified with the NMIFLTC.NFCLKSEL[1:0] bits. When the
sampled level matches three times, the output level from the digital filter changes.
For details of the digital filter, see section 14.4.7, Digital Filter .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — NMIMD —
0 0 0 0
Description
These bits are read as 0. The write value should be 0.
0: Falling edge
1: Rising edge
These bits are read as 0. The write value should be 0.
b5 b4 b3 b2
— — — —
0 0 0 0
b1 b0
— —
0 0
b1 b0
NFLTE
—
N
0 0
Description
0: Digital filter is disabled
1: Digital filter is enabled
These bits are read as 0. The write value should be 0.
14. Interrupt Controller (ICUb)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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