Priority Interrupt Bit - Renesas RX100 Series User Manual

RX13T Group
23.10.3.1

Priority Interrupt Bit

Figure 23.67 shows an example of operation in Start Frame reception where a priority interrupt bit is in use. Setting the
CR1.PIBE bit to 1 enables the use of a priority interrupt bit.
Operations of the extended serial mode control section in start Frame reception where a priority interrupt bit is in use are
as described below.
Steps (1) to (4) are the same as in Figure 23.63 , for Start Frame reception.
(5) If the value of the bit selected by the CR1.PIBS[2:0] bits matches the corresponding bit in the PCF1DR register, the
STR.PIBDF flag is set to 1. An SCIX1 interrupt is also generated if the value of the ICR.PIBDIE bit is 1. Transfer of
the Information Frame starts after that. If the data received in Control Field 1 do not match the data set in either or
both of registers PCF1DR and SCF1DR and the priority interrupt bit is not detected, a transition to the state prior to
Break Field low width detection proceeds.
RXDX12 pin
CR0.RXDSF
Specified period for
TCNT and TPRE
STR.BFDF
STR.CF0MF
STR.PIBDF
(1)
The above diagram assumes the following:
ESMER: ESME = 1
CR1: BFE = 1, PIBE = 1, CF0RE = 0, CF1DS[1:0] = 10b, PIBS[2:0] = 011b
PCR: RXDXPS = 0
ICR: BFDIE = 1, CF0MIE = 1, PIBDIE = 1
TMR: TOMS[1:0] = 01b
Figure 23.67 Example of Operations When Receiving a Start Frame While the CR1.PIBE Bit is 1
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Break Field low width
Write 1 to
Set to 0 after Break Field
CR3.SDST
low width detection
(2) (3)
23. Serial Communications Interface (SCIg, SCIh)
Start Frame
Control Field 0
8 bits
Write 1 to
STCR.BFDCL
(4)
Information Frame
Control Field 1
The bit specified by PIBS[2:0] in CR1
matches the value set in PCF1DR.
Write 1 to
STCR.CF0MCL
Write 1 to
STCR.PIBDCL
(5)
Data Field
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