Port Output Enable Control Register 5 (Poecr5) - Renesas RX100 Series User Manual

RX13T Group
20.2.11

Port Output Enable Control Register 5 (POECR5)

Address(es): POE.POECR5 0008 C4D2h
b15 b14
— —
Value after reset: 0 0
Bit Symbol
b0 CMADDMT0ZE
b1 IC1ADDMT0ZE
b2 —
b3 —
b4 IC4ADDMT0ZE
b15 to b5 —
Note 1. Can be modified only once after a reset.
The POECR5 register is used to extend the control conditions to put the output of the MTU0 pins in the high-impedance
state.
CMADDMT0ZE Bit (MTU0 High-Impedance Condition CFLAG Add)
Adds the POECMPFR.CnFLAG flag (n = 0 to 2) to the high-impedance control conditions for the MTU0 pin
(MTIOC0A, MTIOC0B, MTIOC0C, MTIOC0D).
However, when the pins are in the high-impedance state by the flag, an OEIn interrupt (n = 1, 3, 4) will not be generated.
IC1ADDMT0ZE Bit (MTU0 High-Impedance Condition POE0F Add)
Adds the ICSR1.POE0F flag to the high-impedance control conditions for the MTU0 pin (MTIOC0A, MTIOC0B,
MTIOC0C, MTIOC0D).
IC4ADDMT0ZE Bit (MTU0 High-Impedance Condition POE10F Add)
Adds the ICSR4.POE10F flag to the high-impedance control conditions for the MTU0 pin (MTIOC0A, MTIOC0B,
MTIOC0C, MTIOC0D).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— — — —
0 0 0 0
Bit Name
MTU0 High-Impedance
Condition CFLAG Add
MTU0 High-Impedance
Condition POE0F Add
Reserved
Reserved
MTU0 High-Impedance
Condition POE10F Add
Reserved
b9 b8 b7 b6
— — — —
0 0 0 0
Description
0: Does not add the flags to the conditions to put the output in
the high-impedance state.
1: Adds the flags to the conditions to put the output in the
high-impedance state.
0: Does not add the flag to the conditions to put the output in
the high-impedance state.
1: Adds the flag to the conditions to put the output in the high-
impedance state.
This bit is read as 0. The write value should be 0.
This bit is read as 1. The write value should be 1.
0: Does not add the flag to the conditions to put the output in
the high-impedance state.
1: Adds the flag to the conditions to put the output in the high-
impedance state.
These bits are read as 0. The write value should be 0.
20. Port Output Enable 3 (POE3C)
b5 b4 b3 b2
IC4ADD IC1ADD
— — —
MT0ZE MT0ZE
0 0 1 0
Page 542 of 1041
b1 b0
CMADD
MT0ZE
0 0
R/W
1
R/W*
1
R/W*
R/W
R/W
1
R/W*
R/W