Usage Notes; I/O Port States; Module Stop State Of Dtc; On-Chip Peripheral Module Interrupts - Renesas RX100 Series User Manual

RX13T Group
11.7

Usage Notes

11.7.1

I/O Port States

I/O port states are retained in software standby mode. Therefore, the supply current is not reduced if output signals are
high level.
11.7.2

Module Stop State of DTC

Before setting the MSTPCRA.MSTPA28 bit to 1, set the DTCST.DTCST bit of the DTC to 0 to avoid activating the
DTC.
For details, refer to section 16, Data Transfer Controller (DTCb) .
11.7.3

On-Chip Peripheral Module Interrupts

Interrupts do not operate in the module stop state. Therefore, if the module stop state is made after an interrupt request is
generated, a CPU interrupt source or a DTC startup source cannot be cleared. For this reason, disable interrupts before
entering the module stop state.
11.7.4

Write Access to MSTPCRA, MSTPCRB, and MSTPCRC

Write accesses to MSTPCRA, MSTPCRB, and MSTPCRC should be made only by the CPU.
11.7.5

Timing of WAIT Instructions

The WAIT instruction is executed before completion of the preceding register write. The WAIT instruction being
executed before the register setting is modified may cause unintended operation. To avoid this, always execute the WAIT
instruction after confirming that the last register setting is done.
11.7.6

Rewrite the Register by DTC in Sleep Mode

Depending on the settings of the OFS0.IWDTSLCSTP bit and IWDTCSTPR.SLCSTP bit, the IWDT may also stop in
sleep mode. To avoid this, do not set up the DTC to rewrite any registers related to the IWDT in sleep mode.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
11. Low Power Consumption
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