Master Receive Operation - Renesas RX100 Series User Manual

RX13T Group
7 8 9
SCL0
SDA0
b1 b0 ACK
DATA n-2
BBSY
MST
TRS
Transmit data (DATA n-1)
TDRE
TEND
RDRF
DATA n-1
ICDRT
ICDRS DATA n-2
ICDRR
ACKBT
ACKBR
STOP
SP
Write data to ICDRT register
(Final transmit data [DATA n])
Figure 24.9 Master Transmit Operation Timing (3)
24.3.4

Master Receive Operation

In master receive operation, the RIIC as a master device outputs the SCL clock, receives data from the slave device, and
returns acknowledgments. Because the RIIC must start by sending a slave address to the corresponding slave device, this
part of the procedure is performed in master transmit mode, but the subsequent steps are in master receive mode.
Figure 24.10 and Figure 24.11 show examples of usage of master reception (7-bit address format) and Figure 24.12 to
Figure 24.14 show the timing of operations in master reception.
The following describes the procedure and operations for master reception.
(1) Initial settings. For details, refer to section 24.3.2, Initial Settings .
(2) Read the ICCR2.BBSY flag to check that the bus is open, and then set the ICCR2.ST bit to 1 (start condition
issuance request). Upon receiving the request, the RIIC issues a start condition. When the RIIC detects the start
condition, the BBSY flag and the ICSR2.START flag are automatically set to 1 and the ST bit is automatically set to
0. At this time, if the start condition is detected and the levels for the SDA output and the levels on the SDA0 line
have matched while the ST bit is 1, the RIIC recognizes that issuing of the start condition as requested by the ST bit
has been successfully completed, and bits MST and TRS in the ICCR2 register are automatically set to 1, placing
the RIIC in master transmit mode. The ICSR2.TDRE flag is also automatically set to 1 in response to setting of the
TRS bit to 1.
(3) Check that the ICSR2.TDRE flag is 1, and then write the value for transmission (the first byte indicates the slave
address and value of the R/W# bit) to the ICDRT register. Once the data for transmission are written to the ICDRT
register, the TDRE flag is automatically set to 0, the data are transferred from the ICDRT register to the ICDRS
register, and the TDRE flag is again set to 1. Once the byte containing the slave address and R/W# bit has been
transmitted, the value of the ICCR2.TRS bit is automatically updated to select transmit or receive mode in accord
with the value of the transmitted R/W# bit. If the value of the R/W# bit was 1, the TRS bit is set to 0 on the rising
edge of the ninth cycle of SCL clock, placing the RIIC in master receive mode. At this time, the TDRE flag is set to
0 and the ICSR2.RDRF flag is automatically set to 1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
1 2 3 4 5 6
b7 b6 b5 b4 b3 b2
DATA n-1
DATA n-1
0 (ACK)
[4]
7 8 9 1 2 3
b1 b0 ACK b7 b6 b5
Transmit data (DATA n)
DATA n
XXXX (Initial value/final receive data)
0 (ACK)
0 (ACK)
2
24. I C-bus Interface (RIICa)
4 5 6 7 8 9
b4 b3 b2 b1 b0 A/NA
DATA n
DATA n
X (ACK/NACK)
Write 1
to SP bit
P
Clear
STOP flag
[5] [7]
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