Limitations On Simple Spi Mode - Renesas RX100 Series User Manual

RX13T Group
23.13.11

Limitations on Simple SPI Mode

(1) Master Mode
 Use a resistor to pull up or pull down the clock line matching the initial settings for the transfer clock set by the
SPMR.CKPH and CKPOL bits when the SPMR.SSE bit is 1.
This prevents the clock line from being placed in the high-impedance state when the SCR.TE bit is set to 0 or
unexpected edges from being generated on the clock line when the SCR.TE bit is changed from 0 to 1. When the
SPMR.SSE bit is 0 in single master mode, pulling up or pulling down the clock line is not necessary because the
clock line is not placed in the high-impedance state even when the SCR.TE bit is set to 0.
 In the case of the setting for clock delay (SPMR.CKPH bit is 1), the receive data full interrupt (RXI) is generated
before the final clock edge on the SCKn pin as indicated in Figure 23.80 . If the TE and RE bits in the SCR become
0 at this time before the final edge of the clock signal on the SCKn pin, the SCKn pin is placed in the
high-impedance state, so the width of the last clock pulse of the transfer clock is shortened. Furthermore, an RXI
interrupt may lead to the input signal on the SSn# pin of a connected slave going to the high level before the final
edge of the clock signal on the SCKn pin, leading to incorrect operation of the slave.
 In a multi-master configuration, take care because the SCKn pin output becomes high-impedance while the input on
the SSn# pin is at the low level if a mode fault error occurs as the current character is being transferred, stopping
supply of the clock signal to the connected slave. Remake the settings for the connected slave to avoid misaligned
bits when transfer is restarted.
SCKn pin
(SPMR.CKPOL = 0)
SCKn pin
(SPMR.CKPOL = 1)
RXDn pin
RXI source
Figure 23.80 Timing of the RXI Interrupt in Simple SPI Mode (with Clock Delay)
(2) Slave Mode
 Secure at least five cycles of the PCLK from writing transmit data in the TDR register to start of the external clock
input. Also secure at least five cycles of the PCLK from input of low level on the SSn# pin to start of the external
clock input.
 Provide an external clock signal from the master the same as the transmit/receive data length.
 Control the input on the SSn# pin before the start and after the end of data transfer.
 When the level being input on the SSn# pin is to be changed from low to high while the current character is being
transferred, set the TE and RE bits in the SCR to 0 and, after remaking the settings, restart transfer of the first byte.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Bit 0 Bit 1 Bit 2
23. Serial Communications Interface (SCIg, SCIh)
Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
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