Renesas RX100 Series User Manual page 578

RX13T Group
Figure 22.6 shows the IWDT refresh-operation waveforms when PCLK > IWDTCLK and clock divide ratio =
IWDTCLK.
Peripheral module
clock (PCLK)
IWDT-dedicated
clock (IWDTCLK)
Data written to
IWDTRR register
IWDTRR register write
signal (internal signal)
IWDTRR register FFh
Refresh
synchronization signal
Refresh signal
(after synchronization
with IWDTCLK)
Counter value
Figure 22.6 IWDT Refresh Operation Waveforms (IWDTCR.CKS[3:0] = 0000b, IWDTCR.TOPS[1:0] = 11b)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
00h 54h 00h
00h FFh
Invalid
n+2 n+1
22. Independent Watchdog Timer (IWDTa)
FFh
Valid
00h FFh
Refresh request
n n-1 n-2 n-3 07FFh
Refreshing
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