Operating Power Control Register (Opccr) - Renesas RX100 Series User Manual

RX13T Group
11.2.5

Operating Power Control Register (OPCCR)

Address(es): 0008 00A0h
b7 b6
— —
0 0
Value after reset:
Bit Symbol
b2 to b0 OPCM[2:0]
b3 —
b4 OPCMTSF
b7 to b5 —
Note: Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
The OPCCR register is used to reduce power consumption in normal operating mode, sleep mode, and deep sleep mode.
Power consumption can be reduced according to the operating frequency and operating voltage to be used by the OPCCR
setting.
The OPCCR register cannot be rewritten under the following conditions:
 When the OPCCR.OPCMTSF flag is 1 (during transition)
 Time period from WAIT instruction execution for a sleep mode transition, until exit from sleep mode to normal
operation
 Time period from WAIT instruction execution for a deep sleep mode transition, until exit from deep sleep mode to
normal operation
The OPCCR register cannot be rewritten while the flash memory is being programmed or erased (P/E).
For the procedures of changing operating power control modes, refer to Function in section 11.5, Function for Lower
Operating Power Consumption .
During sleep mode or mode transitions, do not write to the registers related to system control (indicated by 'SYSTEM' in
the Module Symbol column in Table 5.1, List of I/O Registers (Address Order) ).
OPCM[2:0] Bits (Operating Power Control Mode Select)
The OPCM[2:0] bits select operating power control mode in normal operating mode, sleep mode, and deep sleep mode.
Table 11.3 shows the relationship between operating power control modes, the OPCM[2:0] bit settings, and the
operating frequency and voltage ranges.
OPCMTSF Flag (Operating Power Control Mode Transition Status Flag)
This flag indicates the switching control state during and after operating power mode transition.
This flag becomes 1 when the value of the OPCM[2:0] bits is rewritten, and 0 when mode transition is completed. Read
this flag and confirm that it is 0 before proceeding to the next processing. Only rewrite the OPCM[2:0] bits when this
flag is 0.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
OPCM
— —
TSF
0 0 0 0
Bit Name Description
Operating Power Control
b2
0 0 0: High-speed operating mode
Mode Select
0 1 0: Middle-speed operating mode
Settings other than above are prohibited.
Reserved This bit is read as 0. The write value should be 0.
Operating Power Control 0: Transition completed
Mode Transition Status 1: During transition
Flag
Reserved These bits are read as 0. The write value should be 0.
b1 b0
OPCM[2:0]
1 0
b0
11. Low Power Consumption
R/W
R/W
R/W
R
R/W
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