Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
Page 3 Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 4 RX Family R01AN1411EJ Hardware Design Guide Examples of register initial setting RX13T Group — Initial Setting Examples Examples of applications and sample programs — — Renesas Technical Preliminary report on the specifications of a product, — — Update document, etc.
Page 5 2. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. X.X.X ...
Page 6 3. List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communications Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus Input/Output IrDA Infrared Data Association...
Page 7: Table Of Contents
Contents Features ..............................31 Overview ............................32 Outline of Specifications ........................32 List of Products ............................ 36 Block Diagram ............................. 37 Pin Functions ............................38 Pin Assignments ..........................40 CPU ............................... 44 Features ..............................44 Register Set of the CPU ........................45 2.2.1 General-Purpose Registers (R0 to R15) ..................
Page 8 Pipeline ..............................63 2.8.1 Overview ............................ 63 2.8.2 Instructions and Pipeline Processing ..................65 2.8.2.1 Instructions Converted into Single Micro-Operation and Pipeline Processing ....65 2.8.2.2 Instructions Converted into Multiple Micro-Operations and Pipeline Processing .... 67 2.8.2.3 Pipeline Basic Operation ....................70 2.8.3 Calculation of the Instruction Processing Time .................
Page 9 7.2.1 Option Function Select Register 0 (OFS0) ................107 7.2.2 Option Function Select Register 1 (OFS1) ................109 7.2.3 Endian Select Register (MDE) ....................110 Usage Note ............................111 7.3.1 Setting Example of Option-Setting Memory ................111 Voltage Detection Circuit (LVDAb) ....................112 Overview ............................
Page 10 9.2.16 High-Speed On-Chip Oscillator Trimming Register n (HOCOTRRn) (n = 0) ......147 Main Clock Oscillator ........................148 9.3.1 Connecting a Crystal ........................ 148 9.3.2 External Clock Input ......................... 149 9.3.3 Notes on the External Clock Input ................... 149 Oscillation Stop Detection Function ....................150 9.4.1 Oscillation Stop Detection and Operation after Detection ............
Page 11 11.2.2 Module Stop Control Register A (MSTPCRA) ................ 172 11.2.3 Module Stop Control Register B (MSTPCRB) ................ 173 11.2.4 Module Stop Control Register C (MSTPCRC) ................ 174 11.2.5 Operating Power Control Register (OPCCR) ................175 11.3 Reducing Power Consumption by Switching Clock Signals ............. 177 11.4 Module Stop Function ........................
Page 12 13.3.2 Vector and Site for Saving the Values in the PC and PSW ............193 13.4 Hardware Processing for Accepting and Returning from Exceptions ..........194 13.5 Hardware Pre-Processing ........................195 13.5.1 Undefined Instruction Exception ....................195 13.5.2 Privileged Instruction Exception ....................195 13.5.3 Floating-Point Exception ......................
Page 13 14.4.4 Determining Priority ......................... 227 14.4.5 Multiple Interrupts ........................227 14.4.6 Fast Interrupt ..........................227 14.4.7 Digital Filter ..........................228 14.4.8 External Pin Interrupts ......................228 14.5 Non-maskable Interrupt Operation ....................229 14.6 Return from Power-Down States ....................... 230 14.6.1 Return from Sleep Mode or Deep Sleep Mode ................
Page 14 16.2.4 DTC Transfer Source Register (SAR) ..................252 16.2.5 DTC Transfer Destination Register (DAR) ................252 16.2.6 DTC Transfer Count Register A (CRA) ................... 253 16.2.7 DTC Transfer Count Register B (CRB) ................... 254 16.2.8 DTC Control Register (DTCCR) ....................254 16.2.9 DTC Vector Base Register (DTCVBR) ...................
Page 15 I/O Ports ............................293 17.1 Overview ............................293 17.2 I/O Port Configuration ........................295 17.3 Register Descriptions ......................... 297 17.3.1 Port Direction Register (PDR) ....................297 17.3.2 Port Output Data Register (PODR) ..................298 17.3.3 Port Input Data Register (PIDR) ....................299 17.3.4 Port Mode Register (PMR) .......................
Page 16 19.2.7 Timer Compare Match Clear Register (TCNTCMPCLR) ............348 19.2.8 Timer Interrupt Enable Register (TIER) .................. 349 19.2.9 Timer Status Register (TSR) ....................352 19.2.10 Timer Buffer Operation Transfer Mode Register (TBTM) ............353 19.2.11 Timer Input Capture Control Register (TICCR) ..............354 19.2.12 Timer Counter (TCNT) ......................
Page 17 19.3.4 Cascaded Operation ........................399 19.3.5 PWM Modes ..........................404 19.3.6 Phase Counting Mode ....................... 408 19.3.6.1 16-Bit Phase Counting Mode ..................408 19.3.6.2 Cascade Connection 32-Bit Phase Counting Mode ............419 19.3.7 Reset-Synchronized PWM Mode ..................... 420 19.3.8 Complementary PWM Mode ....................423 19.3.9 A/D Converter Start Request Delaying Function ..............
Page 18 19.6.19 Note on Transition from Normal Mode or PWM Mode 1 to Reset-Synchronized PWM Mode ..................494 19.6.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode .... 494 19.6.21 Simultaneous Input Capture in MTU1.TCNT and MTU2.TCNT in Cascade Connection ..494 19.6.22 Interrupt Skipping Function 2 ....................
Page 19 20.6.1 Transition to Low Power Consumption Mode ................. 556 20.6.2 High-Impedance Control When the MTU is Not Selected ............556 20.6.3 When the POE is Not Used ...................... 556 Compare Match Timer (CMT) ...................... 557 21.1 Overview ............................557 21.2 Register Descriptions .........................
Page 20 22.4.1 Refresh Operations ........................581 22.4.2 Clock Divide Ratio Setting ....................... 581 Serial Communications Interface (SCIg, SCIh) ................582 23.1 Overview ............................582 23.2 Register Descriptions ......................... 588 23.2.1 Receive Shift Register (RSR) ....................588 23.2.2 Receive Data Register (RDR) ....................588 23.2.3 Receive Data Register H, L, HL (RDRH, RDRL, RDRHL) ............
Page 21 23.2.37 Timer Mode Register (TMR) ....................634 23.2.38 Timer Prescaler Register (TPRE) ..................... 635 23.2.39 Timer Count Register (TCNT) ....................635 23.3 Operation in Asynchronous Mode ..................... 636 23.3.1 Serial Data Transfer Format ..................... 636 23.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ....638 23.3.3 Clock ............................
Page 22 23.8.2 SS Function in Master Mode ....................691 23.8.3 SS Function in Slave Mode ...................... 691 23.8.4 Relationship between Clock and Transmit/Receive Data ............692 23.8.5 SCI Initialization (Simple SPI Mode) ..................693 23.8.6 Transmission and Reception of Serial Data (Simple SPI Mode) ..........693 23.9 Bit Rate Modulation Function ......................
Page 23 C-bus Interface (RIICa) ......................724 24.1 Overview ............................724 24.2 Register Descriptions ......................... 727 24.2.1 C-bus Control Register 1 (ICCR1) ..................727 24.2.2 C-bus Control Register 2 (ICCR2) ..................729 24.2.3 C-bus Mode Register 1 (ICMR1) ..................733 24.2.4 C-bus Mode Register 2 (ICMR2) ..................734 24.2.5 C-bus Mode Register 3 (ICMR3) ..................
Page 24 24.9.2 Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) ....787 24.9.3 Slave Arbitration-Lost Detection (SALE Bit) ................788 24.10 Start Condition/Restart Condition/Stop Condition Issuing Function ..........789 24.10.1 Issuing a Start Condition ......................789 24.10.2 Issuing a Restart Condition ....................... 789 24.10.3 Issuing a Stop Condition ......................
Page 25 26.2.6 A/D Channel Select Register C0 (ADANSC0) ................ 821 26.2.7 A/D-Converted Value Addition/Average Function Channel Select Register 0 (ADADS0) ..822 26.2.8 A/D-Converted Value Addition/Average Count Select Register (ADADC) ......823 26.2.9 A/D Control Extended Register (ADCER) ................824 26.2.10 A/D Conversion Start Trigger Select Register (ADSTRGR) ...........
Page 26 26.3.11 Programmable Gain Amplifier ....................877 26.4 Interrupt Sources and DTC Transfer Requests .................. 878 26.4.1 Interrupt Requests ........................878 26.5 Allowable Impedance of Signal Source .................... 878 26.6 Usage Notes ............................879 26.6.1 Notes on Reading Data Registers ..................... 879 26.6.2 Notes on Stopping A/D Conversion ..................
Page 27 28.3.5 Comparator Setting Flowchart ....................898 28.4 Usage Notes ............................899 28.4.1 Module Stop Function Setting ....................899 28.4.2 Comparator C Operation in Module Stop State ................ 899 28.4.3 Comparator C Operation in Software Standby Mode .............. 899 28.4.4 Comparator Operation while the 12-Bit A/D Convertor is in the Module-Stop State ..... 899 28.4.5 Setting the D/A Converter for Generating Reference Voltage ..........
Page 28 31.4.13 Flash Processing End Address Register H (FEARH) ............... 921 31.4.14 Flash Processing End Address Register L (FEARL) ..............921 31.4.15 Flash Read Buffer Register H (FRBH) ..................922 31.4.16 Flash Read Buffer Register L (FRBL) ..................922 31.4.17 Flash Write Buffer Register H (FWBH) ................... 922 31.4.18 Flash Write Buffer Register L (FWBL) ...................
Page 29 31.9.1 ID Code Protection ........................952 31.9.1.1 Boot Mode ID Code Protection ..................953 31.9.1.2 On-Chip Debugging Emulator ID Code Protection ............954 31.10 Communication Protocol ........................955 31.10.1 State Transition in Boot Mode (SCI Interface) ................ 955 31.10.2 Command and Response Configuration ................... 956 31.10.3 Response to Undefined Commands ..................
Page 30 31.11.7 Procedure to Program the User Area and Data Area ..............981 31.11.8 Procedure to Check Data in the User Area ................982 31.11.9 Procedure to Check Data in the Data Area ................983 31.11.10 Procedure to Set the Access Window in the User Area ............984 31.12 Rewriting by Self-Programming .......................
Page 31: Features
RX13T Group R01UH0822EJ0100 Rev.1.00 Renesas MCUs Jul 31, 2019 32-MHz 32-bit RX MCUs, built-in FPU, 50 DMIPS, power supply 5 V 12-bit ADC (equipped with 3-channel synchronous S/H circuits, programmable gain amplifier × 3 ch, and comparator) 32-MHz PWM (three-phase complementary output × 1 ch), On-chip data flash memory Features ■...
Page 32: Overview
RX13T Group 1. Overview Overview Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type.
Page 33 RX13T Group 1. Overview Table 1.1 Outline of Specifications (2/3) Classification Module/Function Description Interrupt Interrupt controller (ICUb)  Interrupt vectors: 256  External interrupts: 7 (NMI, IRQ0 to IRQ5 pins)  Non-maskable interrupts: 5 (NMI pin, oscillation stop detection interrupt, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and IWDT interrupt) ...
Page 34 RX13T Group 1. Overview Table 1.1 Outline of Specifications (3/3) Classification Module/Function Description Communication Serial communications  3 channels (channel 1 and 5: SCIg, channel 12: SCIh)  SCIg functions interfaces (SCIg, SCIh) Serial communications modes: Asynchronous, clock synchronous, and smart-card interface Multi-processor function On-chip baud rate generator allows selection of the desired bit rate Choice of LSB-first or MSB-first transfer...
Page 35 RX13T Group 1. Overview Table 1.2 Comparison of Functions for Different Packages RX13T Group Module/Functions 48 Pins 32 Pins Interrupts External interrupts NMI, IRQ0 to IRQ5 NMI, IRQ0 to IRQ2, IRQ5 Data transfer controller Available Timers Multi-function timer pulse unit 3 6 channels Port output enable 3 POE0#, POE8#, POE10#...
Page 36: List Of Products
ROM and RAM capacity 5: 128 Kbytes/12 Kbytes 3: 64 Kbytes/12 Kbytes Group name 3T: RX13T Group Series name RX100 Series Type of memory F: Flash memory version Renesas MCU Renesas semiconductor product Figure 1.1 How to Read the Product Part Number R01UH0822EJ0100 Rev.1.00...
Page 37: Block Diagram
RX13T Group 1. Overview Block Diagram Figure 1.2 shows a block diagram. E2 DataFlash IWDTa SCIg × 2 channels SCIh × 1 channel RIICa × 1 channel ICUb MTU3c × 6 channels POE3C Port 1 DTCb CMT × 2 channels (unit 0) Port 2 12-bit A/D converter ×...
Page 38: Pin Functions
RX13T Group 1. Overview Pin Functions Table 1.4 lists the pin functions. Table 1.4 Pin Functions (1/2) Classifications Pin Name Description Power supply Input Power supply pin. Connect it to the system power supply. — Connect this pin to the VSS pin via the 4.7 μF smoothing capacitor used to stabilize the internal power supply.
Page 39 RX13T Group 1. Overview Table 1.4 Pin Functions (2/2) Classifications Pin Name Description  Asynchronous mode/clock synchronous mode Serial communications SCK12 Input/output pin for the clock interface (SCIh) RXD12 Input Input pin for received data TXD12 Output Output pin for transmitted data CTS12# Input Input pin for controlling the start of transmission and reception...
Page 40: Pin Assignments
RX13T Group 1. Overview Pin Assignments Figure 1.3 and Figure 1.4 show the pin assignments. Table 1.5 and Table 1.6 show the lists of pins and pin functions. RX13T Group PLQP0048KB-B (48-pin LFQFP) (Upper perspective view) AVCC0 AVSS0 Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (48-Pin LFQFP)”.
Page 41 RX13T Group 1. Overview 24 23 22 21 20 19 18 17 RX13T Group PLQP0032GB-A (32-pin LQFP) AVCC0 (Upper perspective view) AVSS0 Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (32-Pin LQFP)”. Figure 1.4 Pin Assignments of the 32-Pin LQFP R01UH0822EJ0100 Rev.1.00...
Page 42 RX13T Group 1. Overview Table 1.5 List of Pins and Pin Functions (48-Pin LFQFP) Power Supply, Clock, System Timers Communications Control I/O Port (MTU, POE, CAC) (SCI, RIIC) Others FINED RES# XTAL EXTAL POE10# NMI/IRQ0 MTIOC0D CTS1#/RTS1#/SS1# IRQ5/ADST0 MTIOC0C RXD1/SMISO1/SSCL1 IRQ3 MTIOC0B SCK1...
Page 43 RX13T Group 1. Overview Table 1.6 List of Pins and Pin Functions (32-Pin LQFP) Power Supply, Clock, System Timers Communications Control I/O Port (MTU, POE, CAC) (SCI, RIIC) Others FINED RES# XTAL EXTAL POE10# NMI/IRQ0 MTIOC3C/MTCLKD RXD1/SMISO1/SSCL1/RXD5/SMISO5/ IRQ5 SSCL5 MTIOC1B/MTIOC3A TXD1/SMOSI1/SSDA1/TXD5/SMOSI5/ SSDA5 MTIOC0A/CACREF...
Page 44: Cpu
RX13T Group 2. CPU This MCU has the RX CPU as its core. A variable-length instruction format has been adopted for the RX CPU. Allocating the more frequently used instructions to the shorter instruction lengths facilitates the development of efficient programs that take up less memory. The CPU has 73 basic instructions, 8 floating-point operation instructions, and nine DSP instructions, for a total of 90 instructions.
Page 45: Register Set Of The Cpu
RX13T Group 2. CPU Register Set of the CPU The RX CPU has 16 general-purpose registers, nine control registers, and one accumulator used for DSP instructions. General-purpose registers R0 (SP) Control registers (Interrupt stack pointer) (User stack pointer) INTB (Interrupt table register) (Program counter) (Processor status word) (Backup PC)
Page 46: General-Purpose Registers (R0 To R15)
RX13T Group 2. CPU 2.2.1 General-Purpose Registers (R0 to R15) This CPU has 16 general-purpose registers (R0 to R15). R0 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW).
Page 47: Interrupt Stack Pointer (Isp)/User Stack Pointer (Usp)
RX13T Group 2. CPU 2.2.2.1 Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) Value after reset: Value after reset: The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP). Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the processor status word (PSW).
Page 48: Processor Status Word (Psw)
RX13T Group 2. CPU 2.2.2.4 Processor Status Word (PSW) — — — — IPL[3:0] — — — — — Value after reset: — — — — — — — — — — — — Value after reset: Symbol Bit Name Description Carry Flag 0: No carry has occurred.
Page 49: Backup Pc (Bpc)
RX13T Group 2. CPU The processor status word (PSW) indicates the results of instruction execution or the state of the CPU. C Flag (Carry Flag) This flag indicates whether a carry, borrow, or shift-out has occurred as the result of an operation. Z Flag (Zero Flag) This flag indicates that the result of an operation was 0.
Page 50: Backup Psw (Bpsw)
RX13T Group 2. CPU 2.2.2.6 Backup PSW (BPSW) Value after reset: Undefined The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW.
Page 51 RX13T Group 2. CPU Symbol Bit Name Description 0 Flush Bit of Denormalized Number 0: A denormalized number is handled as a denormalized number. 1: A denormalized number is handled as 0.* — Reserved This bit is read as 0. The write value should be 0. Invalid Operation Exception Enable 0: Invalid operation exception is masked.
Page 52 RX13T Group 2. CPU  Rounding towards –: An inexact result is rounded to the nearest available value in the direction of negative infinity. (1) Rounding to the nearest value is specified as the default mode and returns the most accurate value. (2) Modes such as rounding towards 0, rounding towards +, and rounding towards –...
Page 53: Register Associated With Dsp Instructions
RX13T Group 2. CPU 2.2.3 Register Associated with DSP Instructions 2.2.3.1 Accumulator (ACC) Range for reading by MVFACMI b48 b47 b16 b15 Range for reading and writing by MVTACHI and MVFACHI Range for writing by MVTACLO Undefined Value after reset: The accumulator (ACC) is a 64-bit register used for DSP instructions.
Page 54: Processor Mode
RX13T Group 2. CPU Processor Mode The RX CPU supports two processor modes, supervisor and user. These processor modes enable the realization of a hierarchical CPU resource protection. Each processor mode imposes a level on rights of access to the CPU resources and the instructions that can be executed. Supervisor mode carries greater rights than those of user mode.
Page 55: Data Types
RX13T Group 2. CPU Data Types The RX CPU can handle four types of data: integer, floating-point, bit, and string. For details, refer to RX Family User's Manual: Software. Endian For the RX CPU, instructions are little endian, but the data arrangement is selectable as little or big endian. 2.5.1 Switching the Endian As arrangements of bytes, this MCU supports both big endian, where the higher-order byte (MSB) is at location 0, and...
Page 56 RX13T Group 2. CPU Table 2.3 32-Bit Write Operations when Little Endian has been Selected Operation Address Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit of dest to address 0 to address 1 to address 2 to address 3...
Page 57 RX13T Group 2. CPU Table 2.6 16-Bit Read Operations when Big Endian has been Selected Operation Reading Reading Reading Reading Reading Reading Reading Address a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from...
Page 58 RX13T Group 2. CPU Table 2.10 8-Bit Read Operations when Big Endian has been Selected Operation Reading an 8-bit unit from Reading an 8-bit unit from Reading an 8-bit unit from Reading an 8-bit unit from Address of src address 0 address 1 address 2 address 3...
Page 59: Access To I/O Registers
RX13T Group 2. CPU 2.5.2 Access to I/O Registers The addresses of I/O registers are fixed, and this is regardless of whether the setting is for little endian or big endian. Accordingly, changes to the endian do not affect access to I/O registers. For the arrangements of I/O registers, refer to the descriptions of registers in the relevant sections.
Page 60: Data Arrangement In Memory
RX13T Group 2. CPU 2.5.4.2 Data Arrangement in Memory Data in memory have three sizes: byte (8-bit), word (16-bit), and longword (32-bit). The data arrangement is selectable as little endian or big endian. Figure 2.3 shows the arrangement of data in memory. Data image Data type Address...
Page 61: Vector Table
RX13T Group 2. CPU Vector Table There are two types of vector table: fixed and relocatable. Each vector in the vector table consists of 4 bytes and specifies the address where the corresponding exception handling routine starts. 2.6.1 Fixed Vector Table The fixed vector table is allocated to a fixed address range.
Page 62: Relocatable Vector Table
RX13T Group 2. CPU 2.6.2 Relocatable Vector Table The address where the relocatable vector table is placed can be adjusted. The table is a 1,024-byte region that contains all vectors for unconditional traps and interrupts and starts at the address (IntBase) specified in the interrupt table register (INTB).
Page 63: Operation Of Instructions
RX13T Group 2. CPU Operation of Instructions 2.7.1 Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions The RMPA instruction and the string-manipulation instructions except the SSTR instruction (that is, SCMPU, SMOVB, SMOVF, SMOVU, SUNTIL, and SWHILE instructions) may prefetch data from the memory to speed up the read processing.
Page 64 RX13T Group 2. CPU (5) WB stage (write-back stage) The operation result and the data read from memory are written to the register (RW) in the WB stage. The data read from memory and the other type of data, such as the operation result, can be written to the register in the same clock cycles. Figure 2.6 shows the pipeline configuration and its operation.
Page 65: Instructions And Pipeline Processing
RX13T Group 2. CPU 2.8.2 Instructions and Pipeline Processing The operands in the table below indicate the following meaning. #IMM: Immediate flag: bit, flag Rs, Rs2, Rd, Rd2, Ri, Rb: General-purpose register CR: Control register dsp: displacement pcdsp: displacement 2.8.2.1 Instructions Converted into Single Micro-Operation and Pipeline Processing The table below lists the instructions that are converted into a single micro-operation.
Page 66 RX13T Group 2. CPU Figure 2.7 to Figure 2.9 show the operation of instructions that are converted into a basic single micro-operation. 4 stages ADD R1, R2 Note: Multi-cycle instructions (DIV, DIVU) are executed in multiple cycles in the E stage. DIV R3, R4 Figure 2.7 Operation for Register-Register, Immediate-Register...
Page 67: Instructions Converted Into Multiple Micro-Operations And Pipeline Processing
RX13T Group 2. CPU 2.8.2.2 Instructions Converted into Multiple Micro-Operations and Pipeline Processing The table below lists the instructions that are converted into multiple micro-operations. The number of cycles in the table indicates the number of cycles during no-wait memory access. Table 2.14 Instructions that are Converted into Multiple Micro-Operations (1/2) Mnemonic (indicates the common operation when...
Page 68 RX13T Group 2. CPU Table 2.14 Instructions that are Converted into Multiple Micro-Operations (2/2) Mnemonic (indicates the common operation when Reference Instruction the size is omitted) Figure Number of Cycles  SCMPU String manipulation instructions* — 2+4×floor(n/4)+4×(n%4) n: Number of comparison bytes* ...
Page 69 RX13T Group 2. CPU Figure 2.10 to Figure 2.14 show the operation of instructions that are converted into basic multiple micro-operations. Note: mop: Micro-operation, stall: Pipeline stall Bypass process ADD [R1], R2 (mop1) load stall (mop2) add Figure 2.10 Arithmetic/Logic Instruction (Memory Source Operand) Load data Bit manipulation, store operation...
Page 70: Pipeline Basic Operation
RX13T Group 2. CPU 2.8.2.3 Pipeline Basic Operation In the ideal pipeline processing, each stage is executed in one cycle, though all instructions may not be pipelined in due to the processing in each stage and the branch execution. The CPU controls the pipeline stage with the IF stage in the unit of instructions, while the D and subsequent stages in the unit of micro-operations.
Page 71 RX13T Group 2. CPU (2) Pipeline Flow with no Stall (a) Bypass process Even when the result of the preceding instruction will be used in a subsequent instruction, the operation processing between registers is pipelined in by the bypass process. ADD R1, R2 (mop) add Bypass process...
Page 72: Calculation Of The Instruction Processing Time
RX13T Group 2. CPU (d) When the load data is not used by the subsequent instruction When the load data is not used by the subsequent instruction, the subsequent operations are in fact executed earlier and the operation processing ends (out-of-order completion). MOV [R1], R2 (mop) load ADD R4, R5...
Page 73: Numbers Of Cycles For Response To Interrupts
RX13T Group 2. CPU 2.8.4 Numbers of Cycles for Response to Interrupts Table 2.15 lists numbers of cycles taken by processing for response to interrupts. Table 2.15 Numbers of Cycles for Response to Interrupts Type of Interrupt Request/Details of Processing Fast Interrupt Other Interrupts 2 cycles...
Page 74: Operating Modes
RX13T Group 3. Operating Modes Operating Modes Operating Mode Types and Selection There are two types of operating-mode selection: one is be selected by the level on pins at the time of release from the reset state, and the other is selected by software after release from the reset state. Table 3.1 shows the relationship between levels on the mode-setting pins (MD) on release from the reset state and the operating mode selected at that time.
Page 75: Register Descriptions
RX13T Group 3. Operating Modes Register Descriptions 3.2.1 Mode Monitor Register (MDMONR) Address(es): 0008 0000h — — — — — — — — — — — — — — — Value after reset: 0/1* Note 1. This affects the level on the MD pin at the time of release from the reset state. Symbol Bit Name Description...
Page 76: System Control Register 1 (Syscr1)
RX13T Group 3. Operating Modes 3.2.2 System Control Register 1 (SYSCR1) Address(es): 0008 0008h — — — — — — — — — — — — — — — RAME Value after reset: Symbol Bit Name Description RAME RAM Enable 0: The RAM is disabled.
Page 77: Details Of Operating Modes
RX13T Group 3. Operating Modes Details of Operating Modes 3.3.1 Single-Chip Mode In this mode, all I/O ports can be used as general input/output ports, peripheral function input/output, or interrupt input pins. The chip starts up in single-chip mode if the high level is on the MD pin on release from the reset state. 3.3.2 Boot Mode In this mode, the on-chip flash memory modifying program (boot program) stored in a dedicated area within the MCU...
Page 78: Transitions Of Operating Modes
RX13T Group 3. Operating Modes Transitions of Operating Modes 3.4.1 Operating Mode Transitions Determined by the Mode-Setting Pins Figure 3.1 shows operating mode transitions determined by the settings of the MD pin. Reset MD = High RES# = High RES# = Low MD = Low RES# = Low RES# = High...
Page 79: Address Space
RX13T Group 4. Address Space Address Space Address Space This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figure 4.1 shows the memory maps.
Page 80 RX13T Group 4. Address Space Single-chip mode* 0000 0000h 0000 3000h Reserved area* 0008 0000h Peripheral I/O registers 0010 0000h On-chip ROM (E2 DataFlash) (4 KB) 0010 1000h Reserved area* 007F C000h Peripheral I/O registers 007F C500h Reserved area* 007F FC00h Peripheral I/O registers 0080 0000h Reserved area*...
Page 81: I/O Registers
RX13T Group 5. I/O Registers I/O Registers This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as shown below. Notes on writing to registers are also given below. (1) I/O register addresses (address order) ...
Page 82 RX13T Group 5. I/O Registers  Longword-size I/O registers MOV.L #SFR_ADDR, R1 MOV.L #SFR_DATA, [R1] [R1].L, R1 ;; Next process If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary to read or execute operation for all the registers that were written to.
Page 83: I/O Register Addresses (Address Order)
RX13T Group 5. I/O Registers I/O Register Addresses (Address Order) Table 5.1 List of I/O Registers (Address Order) (1 / 11) Module Number Access Number of Access Reference Address Symbol Register Name Register Symbol of Bits Size Cycles Section 0008 0000h SYSTEM Mode Monitor Register MDMONR...
Page 84 RX13T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (2 / 11) Module Number Access Number of Access Reference Address Symbol Register Name Register Symbol of Bits Size Cycles Section 0008 7300h to Interrupt Source Priority Register 000 to IPR000 to IPR255 2 ICLK section 14.
Page 85 RX13T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (3 / 11) Module Number Access Number of Access Reference Address Symbol Register Name Register Symbol of Bits Size Cycles Section 0008 9008h S12AD A/D-Converted Value Addition/Average Function Channel ADADS0 2 or 3 PCLKB section 26.
Page 86 RX13T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (4 / 11) Module Number Access Number of Access Reference Address Symbol Register Name Register Symbol of Bits Size Cycles Section 0008 A02Dh SCI1 SPI Mode Register SPMR 2 or 3 PCLKB section 23.
Page 87 RX13T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (5 / 11) Module Number Access Number of Access Reference Address Symbol Register Name Register Symbol of Bits Size Cycles Section 0008 B305h SCI12 Receive Data Register 2 or 3 PCLKB section 23.
Page 88 RX13T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (6 / 11) Module Number Access Number of Access Reference Address Symbol Register Name Register Symbol of Bits Size Cycles Section 0008 C02Ah PORTA Port Output Data Register PODR 2 or 3 PCLKB section 17.
Page 89 RX13T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (7 / 11) Module Number Access Number of Access Reference Address Symbol Register Name Register Symbol of Bits Size Cycles Section 0008 C0C2h PORT2 Pull-Up Control Register 2 or 3 PCLKB section 17.
Page 90 RX13T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (8 / 11) Module Number Access Number of Access Reference Address Symbol Register Name Register Symbol of Bits Size Cycles Section 0008 C1B2h PE2 Pin Function Control Register PE2PFS 2 or 3 PCLKB section 18.
Page 91 RX13T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (9 / 11) Module Number Access Number of Access Reference Address Symbol Register Name Register Symbol of Bits Size Cycles Section 0009 5231h Timer Interrupt Skipping Counter 1A TITCNT1A 4 or 5PCLKB section 19.
Page 92 RX13T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (10 / 11) Module Number Access Number of Access Reference Address Symbol Register Name Register Symbol of Bits Size Cycles Section 0009 5386h MTU1 Timer Counter TCNT 4 or 5PCLKB section 19.
Page 93 RX13T Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (11 / 11) Module Number Access Number of Access Reference Address Symbol Register Name Register Symbol of Bits Size Cycles Section 007F C090h FLASH E2 DataFlash Control Register DFLCTL 2 or 3 FCLK section 31.
Page 94: Resets
RX13T Group 6. Resets 6. Resets Overview The following resets are implemented: RES# pin reset, power-on reset, voltage monitoring 0 reset, voltage monitoring 1 reset, voltage monitoring 2 reset, independent watchdog timer reset, and software reset. Table 6.1 lists the reset names and sources. Table 6.1 Reset Names and Sources Reset Name...
Page 95 RX13T Group 6. Resets The internal state and pins are initialized by a reset. Table 6.2 lists the reset targets to be initialized. Table 6.2 Targets Initialized by Each Reset Source Reset Source Voltage Independent Voltage Voltage RES# Pin Power-On Monitoring 0 Watchdog Monitoring 1...
Page 96: Register Descriptions
RX13T Group 6. Resets Register Descriptions 6.2.1 Reset Status Register 0 (RSTSR0) Address(es): 0008 C290h LVD2R LVD1R LVD0R — — — — PORF Value after reset: Symbol Bit Name Description PORF Power-On Reset Detect Flag 0: Power-on reset not detected. R(/W) 1: Power-on reset detected.
Page 97: Reset Status Register 1 (Rstsr1)
RX13T Group 6. Resets LVD2RF Flag (Voltage Monitoring 2 Reset Detect Flag) The LVD2RF flag indicates that VCC voltage has fallen below Vdet2. [Setting condition]  When Vdet2-level VCC voltage is detected. [Clearing conditions]  When a reset listed in Table 6.2 occurs. ...
Page 98: Reset Status Register 2 (Rstsr2)
RX13T Group 6. Resets 6.2.3 Reset Status Register 2 (RSTSR2) Address(es): 0008 00C0h IWDTR — — — — — SWRF — Value after reset: Symbol Bit Name Description IWDTRF Independent Watchdog Timer Reset Detect 0: Independent watchdog timer reset not detected. R(/W) Flag 1: Independent watchdog timer reset detected.
Page 99: Software Reset Register (Swrr)
RX13T Group 6. Resets 6.2.4 Software Reset Register (SWRR) Address(es): 0008 00C2h SWRR[15:0] Value after reset: Symbol Bit Name Description b15 to b0 SWRR[15:0] Software Reset Writing A501h resets the LSI. These bits are read as 0000h. Note: Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register. R01UH0822EJ0100 Rev.1.00 Page 99 of 1041 Jul 31, 2019...
Page 100: Operation
RX13T Group 6. Resets Operation 6.3.1 RES# Pin Reset This is a reset generated by the RES# pin. When the RES# pin is driven low, all the processing in progress is aborted and the LSI enters a reset state. In order to unfailingly reset the LSI, the RES# pin should be held low for the specified power supply stabilization time at a power-on.
Page 101 RX13T Group 6. Resets 4.7 k (reference value) RES# Vdet0 VPOR External voltage RES# pin Voltage monitoring 0 reset state Power-on reset state POR detection signal (Low is valid) LVD0 enable/disable Set by OFS1.LVDAS signal (Low is valid) Voltage detection 0 signal (Low is valid) tPOR tLVD0...
Page 102: Voltage Monitoring 1 Reset And Voltage Monitoring 2 Reset
RX13T Group 6. Resets 6.3.3 Voltage Monitoring 1 Reset and Voltage Monitoring 2 Reset The voltage monitoring 1 reset and voltage monitoring 2 reset are internal resets generated by the voltage monitoring circuit. When the voltage monitoring 1 interrupt/reset enable bit (LVD1RIE) is set to 1 (enabling generation of a reset or interrupt by the voltage detection circuit) and the voltage monitoring 1 circuit mode select bit (LVD1RI) is set to 1 (selecting generation of a reset in response to detection of a low voltage) in the voltage monitoring 1 circuit control register 0 (LVD1CR0), the RSTSR0.LVD1RF flag is set to 1 and the voltage-detection circuit generates a voltage...
Page 103: Independent Watchdog Timer Reset
RX13T Group 6. Resets Vdeti* External voltage RES# pin LVDi valid setting LVCMPCR.LVDiE LVDiCR0.LVDiRN = 0 Voltage detection i signal (Low is valid) RES# pin reset RSTSR0.LVDiRF tLVDi* Internal reset signal LVDiCR0.LVDiRN = 1 Voltage detection i signal (Low is valid) RES# pin reset RSTSR0.LVDiRF tLVDi*...
Page 104: Determination Of Cold/Warm Start
RX13T Group 6. Resets 6.3.6 Determination of Cold/Warm Start By reading the CWSF flag in RSTSR1, the type of reset processing caused can be identified; that is, whether a power-on reset has caused the reset processing (cold start) or a reset signal input during operation has caused the reset processing (warm start).
Page 105: Determination Of Reset Generation Source
RX13T Group 6. Resets 6.3.7 Determination of Reset Generation Source Reading RSTSR0 and RSTSR2 determines which reset was used to execute the reset exception handling. Figure 6.4 shows an example of the flow to identify a reset generation source. Reset exception handling RSTSR2.
Page 106: Option-Setting Memory (Ofsm)
RX13T Group 7. Option-Setting Memory (OFSM) Option-Setting Memory (OFSM) Overview Option-setting memory (OFSM) refers to a set of registers that are provided for selecting the state of the microcontroller after a reset. The option-setting memory is allocated in the ROM. Figure 7.1 shows the option-setting memory area.
Page 107: Register Descriptions
RX13T Group 7. Option-Setting Memory (OFSM) Register Descriptions 7.2.1 Option Function Select Register 0 (OFS0) Address(es): OFSM.OFS0 FFFF FF8Ch — — — — — — — — — — — — — — — — Value after reset: The value set by the user* IWDTS IWDTR IWDTTOPS[1:0] IWDTS...
Page 108 RX13T Group 7. Option-Setting Memory (OFSM) When erasing the block including the OFS0 register, the OFS0 register value becomes FFFF FFFFh. The setting in the OFS0 register is ignored in boot mode, and this register functions similarly when it is set to FFFF FFFFh.
Page 109: Option Function Select Register 1 (Ofs1)
RX13T Group 7. Option-Setting Memory (OFSM) 7.2.2 Option Function Select Register 1 (OFS1) Address(es): OFSM.OFS1 FFFF FF88h — — — — — — — — — — — — — — — — Value after reset: The value set by the user* HOCO —...
Page 110: Endian Select Register (Mde)
RX13T Group 7. Option-Setting Memory (OFSM) 7.2.3 Endian Select Register (MDE) Address(es): OFSM.MDE FFFF FF80h — — — — — — — — — — — — — — — — Value after reset: The value set by the user* —...
Page 111: Usage Note
RX13T Group 7. Option-Setting Memory (OFSM) Usage Note 7.3.1 Setting Example of Option-Setting Memory Since the option-setting memory is allocated in the ROM, values cannot be written by executing instructions. Write appropriate values when writing the program. An example of the settings is shown below. ...
Page 112: Voltage Detection Circuit (Lvdab)
RX13T Group 8. Voltage Detection Circuit (LVDAb) Voltage Detection Circuit (LVDAb) The voltage detection circuit (LVD) monitors the voltage level input to the VCC pin using a program. Overview In voltage detection 0, the detection voltage can be selected from three levels using option function select register 1 (OFS1).
Page 113 RX13T Group 8. Voltage Detection Circuit (LVDAb) Level selection LVDAS circuit (3 levels) Voltage detection 0 reset signal Analog noise filter VDSEL[1:0] Internal reference voltage  Vdet0 (for detecting Vdet0) Level selection LVD1E circuit (9 levels) LVD1CMPE Voltage detection 1 signal Analog noise filter...
Page 114 RX13T Group 8. Voltage Detection Circuit (LVDAb) Voltage monitoring 1 interrupt/reset circuit Voltage detection 1 circuit The setting of the LVD1DET bit will be 0 LVD1SR register LVD1LVL[3:0] if 0 (undetected) is written in the program. LVD1E Level LVD1RIE LVD1CMPE selection LVD1MON bit LVD1RI...
Page 115: Register Descriptions
RX13T Group 8. Voltage Detection Circuit (LVDAb) Register Descriptions 8.2.1 Voltage Monitoring 1 Circuit Control Register 1 (LVD1CR1) Address(es): 0008 00E0h LVD1IR LVD1IDTSEL — — — — — QSEL [1:0] Value after reset: Symbol Bit Name Description b1, b0 LVD1IDTSEL Voltage Monitoring 1 Interrupt b1 b0 0 0: When VCC ≥...
Page 116: Voltage Monitoring 1 Circuit Status Register (Lvd1Sr)
RX13T Group 8. Voltage Detection Circuit (LVDAb) 8.2.2 Voltage Monitoring 1 Circuit Status Register (LVD1SR) Address(es): 0008 00E1h LVD1M LVD1D — — — — — — Value after reset: Symbol Bit Name Description LVD1DET Voltage Monitoring 1 Voltage Change 0: Not detected R/(W) Detection Flag 1: Vdet1 passage detection...
Page 117: Voltage Monitoring 2 Circuit Control Register 1 (Lvd2Cr1)
RX13T Group 8. Voltage Detection Circuit (LVDAb) 8.2.3 Voltage Monitoring 2 Circuit Control Register 1 (LVD2CR1) Address(es): 0008 00E2h LVD2IR LVD2IDTSEL — — — — — QSEL [1:0] Value after reset: Symbol Bit Name Description b1, b0 LVD2IDTSEL Voltage Monitoring 2 Interrupt b1 b0 0 0:When VCC ≥...
Page 118: Voltage Monitoring 2 Circuit Status Register (Lvd2Sr)
RX13T Group 8. Voltage Detection Circuit (LVDAb) 8.2.4 Voltage Monitoring 2 Circuit Status Register (LVD2SR) Address(es): 0008 00E3h LVD2M LVD2D — — — — — — Value after reset: Symbol Bit Name Description LVD2DET Voltage Monitoring 2 Voltage Change 0: Not detected R/(W) Detection Flag 1: Vdet2 passage detection...
Page 119: Voltage Monitoring Circuit Control Register (Lvcmpcr)
RX13T Group 8. Voltage Detection Circuit (LVDAb) 8.2.5 Voltage Monitoring Circuit Control Register (LVCMPCR) Address(es): 0008 C297h — LVD2E LVD1E — — — — — Value after reset: Symbol Bit Name Description b4 to b0 — Reserved These bits are read as 0. The write value should be 0. LVD1E Voltage Detection 1 Enable 0: Voltage detection 1 circuit disabled...
Page 120: Voltage Detection Level Select Register (Lvdlvlr)
RX13T Group 8. Voltage Detection Circuit (LVDAb) 8.2.6 Voltage Detection Level Select Register (LVDLVLR) Address(es): 0008 C298h — — LVD2LVL[1:0] LVD1LVL[3:0] Value after reset: Symbol Bit Name Description b3 to b0 LVD1LVL[3:0] Voltage Detection 1 Level Select 0 0 0 0: 4.29 V (Standard voltage during drop in voltage) 0 0 0 1: 4.14 V 0 0 1 0: 4.02 V...
Page 121: Voltage Monitoring 1 Circuit Control Register 0 (Lvd1Cr0)
RX13T Group 8. Voltage Detection Circuit (LVDAb) 8.2.7 Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0) Address(es): 0008 C29Ah LVD1R LVD1C LVD1RI LVD1RI — — — — Value after reset: x: Undefined Symbol Bit Name Description LVD1RIE Voltage Monitoring 1 Interrupt/Reset 0: Disabled Enable 1: Enabled...
Page 122: Voltage Monitoring 2 Circuit Control Register 0 (Lvd2Cr0)
RX13T Group 8. Voltage Detection Circuit (LVDAb) 8.2.8 Voltage Monitoring 2 Circuit Control Register 0 (LVD2CR0) Address(es): 0008 C29Bh LVD2R LVD2C LVD2RI LVD2RI — — — — Value after reset: x: Undefined Symbol Bit Name Description LVD2RIE Voltage Monitoring 2 Interrupt/Reset 0: Disabled Enable 1: Enabled...
Page 123: Vcc Input Voltage Monitor
RX13T Group 8. Voltage Detection Circuit (LVDAb) VCC Input Voltage Monitor 8.3.1 Monitoring Vdet0 Monitoring Vdet0 is not possible. 8.3.2 Monitoring Vdet1 After making the following settings, the LVD1SR.LVD1MON flag can be used to monitor the results of comparison by voltage monitor 1.
Page 124: Reset From Voltage Monitor 0
RX13T Group 8. Voltage Detection Circuit (LVDAb) Reset from Voltage Monitor 0 When using the reset from voltage monitor 0, clear the voltage detection 0 circuit start bit (OFS1.LVDAS) to 0 (enabling the voltage monitor 0 reset after a reset). Figure 8.4 shows an example of operations for a voltage monitoring 0 reset.
Page 125: Interrupt And Reset From Voltage Monitoring 1
RX13T Group 8. Voltage Detection Circuit (LVDAb) Interrupt and Reset from Voltage Monitoring 1 Table 8.2 shows the procedures for setting bits related to the voltage monitoring 1 interrupt and voltage monitoring 1 reset. Table 8.3 shows the procedures for stopping bits related to the voltage monitoring 1 interrupt and voltage monitoring 1 reset.
Page 126 RX13T Group 8. Voltage Detection Circuit (LVDAb) Vdet1 Lower limit on VCC voltage (VCCmin) Set to 0 by a program LVD1DET bit LVD1IDTSEL[1:0] bits are set to 10b (when drop and rise are detected) Voltage monitoring 1 interrupt request Set to 0 by a program LVD1DET bit LVD1IDTSEL[1:0] bits are set to 00b (when rise is detected).
Page 127: Interrupt And Reset From Voltage Monitoring 2
RX13T Group 8. Voltage Detection Circuit (LVDAb) Interrupt and Reset from Voltage Monitoring 2 Table 8.4 shows the procedures for setting bits related to the voltage monitoring 2 interrupt and voltage monitoring 2 reset. Table 8.5 shows the procedure for stopping bits related to the voltage monitoring 2 interrupt and voltage monitoring 2 reset.
Page 128 RX13T Group 8. Voltage Detection Circuit (LVDAb) Vdet2 Lower limit on VCC voltage (VCCmin) Set to 0 by a program LVD2DET bit LVD2IDTSEL[1:0] bits are set to 10b (when drop and rise are detected) Voltage monitoring 2 interrupt request Set to 0 by a program LVD2DET bit LVD2IDTSEL[1:0] bits are set to 00b (when rise is detected).
Page 129: Clock Generation Circuit
RX13T Group 9. Clock Generation Circuit Clock Generation Circuit Overview This MCU incorporates a clock generation circuit. Table 9.1 lists the specifications of the clock generation circuit. Figure 9.1 shows a block diagram of the clock generation circuit. Table 9.1 Specifications of Clock Generation Circuit Item Specification...
Page 130 RX13T Group 9. Clock Generation Circuit SCKCR FCK[3:0] FlashIF clock (FCLK) To FlashIF SCKCR ICK[3:0] PLIDIV[1:0] STC[5:0] System clock (ICLK) PLLCR PLLCR To CPU, DTC, ROM, and RAM Frequency Frequency divider circuit divider CKSEL[2:0] SCKCR PCKB[3:0], PCKD[3:0] SCKCR3 Peripheral module clock (PCLKB, PCLKD) 1/16 To peripheral module...
Page 131: Register Descriptions
RX13T Group 9. Clock Generation Circuit Register Descriptions 9.2.1 System Clock Control Register (SCKCR) Address(es): 0008 0020h FCK[3:0] ICK[3:0] — — — — — — — — Value after reset: — — — — PCKB[3:0] — — — — PCKD[3:0] Value after reset: Symbol Bit Name...
Page 132 RX13T Group 9. Clock Generation Circuit 1. Write to the SCKCR register. 2. Confirm that the value has actually been written to the SCKCR register. 3. Proceed to the next step. PCKD[3:0] Bits (Peripheral Module Clock D (PCLKD) Select) These bits select the frequency of peripheral module clock D (PCLKD). PCKB[3:0] Bits (Peripheral Module Clock B (PCLKB) Select) These bits select the frequency of peripheral module clock B (PCLKB).
Page 133: System Clock Control Register 3 (Sckcr3)
RX13T Group 9. Clock Generation Circuit 9.2.2 System Clock Control Register 3 (SCKCR3) Address(es): 0008 0026h — — — — — CKSEL[2:0] — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 134: Pll Control Register (Pllcr)
RX13T Group 9. Clock Generation Circuit 9.2.3 PLL Control Register (PLLCR) Address(es): 0008 0028h — — STC[5:0] — — — — — — PLIDIV[1:0] Value after reset: Symbol Bit Name Description b1, b0 PLIDIV[1:0] PLL Input Frequency b1 b0 0 0: ×1 Division Ratio Select 0 1: ×1/2 1 0: ×1/4...
Page 135: Pll Control Register 2 (Pllcr2)
RX13T Group 9. Clock Generation Circuit 9.2.4 PLL Control Register 2 (PLLCR2) Address(es): 0008 002Ah — — — — — — — PLLEN Value after reset: Symbol Bit Name Description PLLEN PLL Stop Control 0: PLL is operating. 1: PLL is stopped. b7 to b1 —...
Page 136: Main Clock Oscillator Control Register (Mosccr)
RX13T Group 9. Clock Generation Circuit 9.2.5 Main Clock Oscillator Control Register (MOSCCR) Address(es): 0008 0032h — — — — — — — MOSTP Value after reset: Symbol Bit Name Description MOSTP Main Clock Oscillator Stop 0: Main clock oscillator is operating. 1: Main clock oscillator is stopped.
Page 137: Low-Speed On-Chip Oscillator Control Register (Lococr)
RX13T Group 9. Clock Generation Circuit 9.2.6 Low-Speed On-Chip Oscillator Control Register (LOCOCR) Address(es): 0008 0034h — — — — — — — LCSTP Value after reset: Symbol Bit Name Description LCSTP LOCO Stop 0: LOCO is operating. 1: LOCO is stopped. b7 to b1 —...
Page 138: Iwdt-Dedicated On-Chip Oscillator Control Register (Ilococr)
RX13T Group 9. Clock Generation Circuit 9.2.7 IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR) Address(es): 0008 0035h — — — — — — — ILCSTP Value after reset: Symbol Bit Name Description ILCSTP IWDT-Dedicated On-Chip 0: IWDT-dedicated on-chip oscillator is operating. Oscillator Stop 1: IWDT-dedicated on-chip oscillator is stopped.
Page 139: High-Speed On-Chip Oscillator Control Register (Hococr)
RX13T Group 9. Clock Generation Circuit 9.2.8 High-Speed On-Chip Oscillator Control Register (HOCOCR) Address(es): 0008 0036h — — — — — — — HCSTP Value after reset: Symbol Bit Name Description HCSTP HOCO Stop 0: HOCO is operating. 1: HOCO is stopped. b7 to b1 —...
Page 140: Oscillation Stabilization Flag Register (Oscovfsr)
RX13T Group 9. Clock Generation Circuit 9.2.9 Oscillation Stabilization Flag Register (OSCOVFSR) Address(es): 0008 003Ch MOOV — — — — HCOVF PLOVF — Value after reset: 0/1* Symbol Bit Name Description MOOVF Main Clock Oscillation 0: Main clock is stopped Stabilization Flag 1: Oscillation is stable and the clock can be used as the system clock* —...
Page 141 RX13T Group 9. Clock Generation Circuit supply of the HOCO clock is started to the MCU internally. [Clearing condition]  After the HOCOCR.HCSTP bit is set to 1, the processing to stop the oscillation of the HOCO is completed. R01UH0822EJ0100 Rev.1.00 Page 141 of 1041 Jul 31, 2019...
Page 142: Oscillation Stop Detection Control Register (Ostdcr)
RX13T Group 9. Clock Generation Circuit 9.2.10 Oscillation Stop Detection Control Register (OSTDCR) Address(es): 0008 0040h OSTDI OSTDE — — — — — — Value after reset: Symbol Bit Name Description OSTDIE Oscillation Stop Detection 0: The oscillation stop detection interrupt is disabled. Oscillation stop Interrupt Enable detection is not notified to the POE.
Page 143: Oscillation Stop Detection Status Register (Ostdsr)
RX13T Group 9. Clock Generation Circuit 9.2.11 Oscillation Stop Detection Status Register (OSTDSR) Address(es): 0008 0041h — — — — — — — OSTDF Value after reset: Symbol Bit Name Description OSTDF Oscillation Stop Detection Flag 0: The main clock oscillation stop has not been detected. R/(W) 1: The main clock oscillation stop has been detected.
Page 144: Main Clock Oscillator Wait Control Register (Moscwtcr)
RX13T Group 9. Clock Generation Circuit 9.2.12 Main Clock Oscillator Wait Control Register (MOSCWTCR) Address(es): 0008 00A2h — — — MSTS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 MSTS[4:0] Main Clock Oscillator Wait Time 0 0 0 0 0: Wait time = 2 cycles (0.5 μs) 0 0 0 0 1: Wait time = 1024 cycles (256 μs) 0 0 0 1 0: Wait time = 2048 cycles (512 μs) 0 0 0 1 1: Wait time = 4096 cycles (1.024 ms)
Page 145: Main Clock Oscillator Forced Oscillation Control Register (Mofcr)
RX13T Group 9. Clock Generation Circuit 9.2.13 Main Clock Oscillator Forced Oscillation Control Register (MOFCR) Address(es): 0008 C293h MOSEL MODR — — — — — — Value after reset: Symbol Bit Name Description b4 to b0 — Reserved These bits are read as 0. The write value should be 0. MODRV21 Main Clock Oscillator Drive 0: 1 MHz or higher and lower than 10 MHz...
Page 146: Low-Speed On-Chip Oscillator Trimming Register (Locotrr)
RX13T Group 9. Clock Generation Circuit 9.2.14 Low-Speed On-Chip Oscillator Trimming Register (LOCOTRR) Address(es): 0008 0060h — — — LOCOTRD[4:0] Value after reset: Symbol Bit Name Description b4 to b0 LOCOTRD[4:0] Low-Speed On-Chip Oscillator 1 0 0 0 0: -16 (Frequency: Low) Frequency Adjustment 1 0 0 0 1: -15 0 1 1 1 0: 14...
Page 147: High-Speed On-Chip Oscillator Trimming Register N (Hocotrrn) (N = 0)
RX13T Group 9. Clock Generation Circuit 9.2.16 High-Speed On-Chip Oscillator Trimming Register n (HOCOTRRn) (n = 0) Address(es): HOCOTRR0 0008 0068h — — HOCOTRD[5:0] Value after reset: Symbol Bit Name Description b5 to b0 HOCOTRD[5:0] High-Speed On-Chip Oscillator 0 0 0 0 0 0: 0 (Frequency: Low) Frequency Adjustment 0 0 0 0 0 1: 1 1 1 1 1 1 0: 62...
Page 148: Main Clock Oscillator
RX13T Group 9. Clock Generation Circuit Main Clock Oscillator There are two ways of supplying the clock signal from the main clock oscillator: connecting an oscillator or the input of an external clock signal. 9.3.1 Connecting a Crystal Figure 9.2 shows an example of connecting a crystal. A damping resistor (R ) should be added, if necessary.
Page 149: External Clock Input
RX13T Group 9. Clock Generation Circuit 9.3.2 External Clock Input Figure 9.4 shows connection of an external clock. Set the MOFCR.MOSEL bit to 1 and open the XTAL pin to operate the oscillator by inputting an external clock signal. EXTAL External clock input Open XTAL...
Page 150: Oscillation Stop Detection Function
RX13T Group 9. Clock Generation Circuit Oscillation Stop Detection Function 9.4.1 Oscillation Stop Detection and Operation after Detection The oscillation stop detection function is used to detect the main clock oscillator stop and to supply LOCO clock pulses from the low-speed on-chip oscillator as the system clock source instead of the main clock. An oscillation stop detection interrupt request can be generated when an oscillation stop is detected.
Page 151: Oscillation Stop Detection Interrupts
RX13T Group 9. Clock Generation Circuit Start Switch to SCKCR3.CKSEL[2:0] = 000b (LOCO) Setting OSTDCR.OSTDIE = 0 Reading OSTDSR.OSTDF = 1 Setting OSTDSR.OSTDF = 0 OSTDSR.OSTDF = 0 Try again? Switch to SCKCR3.CKSEL[2:0] = 010b (main clock oscillator) Note: On return from the oscillation-stopped state, the factor responsible for stopping the main clock oscillation circuit must be removed on the user system to allow the return of oscillation.
Page 152: Pll Circuit
RX13T Group 9. Clock Generation Circuit PLL Circuit The PLL circuit has a function to multiply the frequency from the oscillator. Internal Clock Clock sources of internal clock signals are the main clock, HOCO clock, LOCO clock, PLL clock, and dedicated low-speed clock for the IWDT.
Page 153 RX13T Group 9. Clock Generation Circuit IWDTCLK is internally generated by the IWDT-dedicated on-chip oscillator. R01UH0822EJ0100 Rev.1.00 Page 153 of 1041 Jul 31, 2019...
Page 154: Usage Notes
RX13T Group 9. Clock Generation Circuit Usage Notes 9.7.1 Notes on Clock Generation Circuit (1) The frequencies of the system clock (ICLK), peripheral module clocks (PCLKB, and PCLKD), and FlashIF clock (FCLK) supplied to each module can be selected by the SCKCR register. Each frequency should meet the following: Select each frequency that is within the operation guaranteed range of clock cycle time (t ) specified in AC...
Page 155: Notes On Resonator Connection Pins
RX13T Group 9. Clock Generation Circuit 9.7.4 Notes on Resonator Connection Pins When the main clock is not used, the EXTAL and XTAL pins can be used as general ports P36 and P37. When using these pins as general ports, be sure to stop the main clock (MOSCCR.MOSTP = 1). However, do not use the EXTAL and XTAL pins as general ports P36 and P37 in a system that uses the main clock.
Page 156: Clock Frequency Accuracy Measurement Circuit (Cac)
RX13T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) Clock Frequency Accuracy Measurement Circuit (CAC) 10.1 Overview The clock frequency accuracy measurement circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock to be used as a measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range.
Page 157 RX13T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) DFS[1:0] CACREFE DFS[1:0] CACREF Digital filter RSCS[2:0] RCDS[1:0] EDGES[1:0] 1/32 Measurement 1/128 Edge detection reference circuit 1/1024 clock select circuit 1/8192 Valid edge signal FMCS[2:0] TCSS[1:0] Measurement target clock Main clock CFME HOCO clock Count source...
Page 158: Register Descriptions
RX13T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2 Register Descriptions 10.2.1 CAC Control Register 0 (CACR0) Address(es): 0008 B000h — — — — — — — CFME Value after reset: Symbol Bit Name Description CFME Clock Frequency Measurement Enable 0: Clock frequency measurement is disabled.
Page 159: Cac Control Register 1 (Cacr1)
RX13T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.2 CAC Control Register 1 (CACR1) Address(es): 0008 B001h CACRE EDGES[1:0] TCSS[1:0] FMCS[2:0] Value after reset: Symbol Bit Name Description CACREFE CACREF Pin Input Enable 0: CACREF pin input is disabled. 1: CACREF pin input is enabled.
Page 160: Cac Control Register 2 (Cacr2)
RX13T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.3 CAC Control Register 2 (CACR2) Address(es): 0008 B002h DFS[1:0] RCDS[1:0] RSCS[2:0] Value after reset: Symbol Bit Name Description Reference Signal Select 0: CACREF pin input 1: Internal clock (internally generated signal) b3 to b1 RSCS[2:0] Measurement Reference Clock...
Page 161: Cac Interrupt Request Enable Register (Caicr)
RX13T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.4 CAC Interrupt Request Enable Register (CAICR) Address(es): 0008 B003h OVFFC MENDF FERRF OVFIE MENDI FERRI — — Value after reset: Symbol Bit Name Description FERRIE Frequency Error Interrupt Request 0: Frequency error interrupt request is disabled. Enable 1: Frequency error interrupt request is enabled.
Page 162: Cac Status Register (Castr)
RX13T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.5 CAC Status Register (CASTR) Address(es): 0008 B004h — — — — — OVFF MENDF FERRF Value after reset: Symbol Bit Name Description FERRF Frequency Error Flag 0: The clock frequency is within the range corresponding to the settings.
Page 163: Cac Upper-Limit Value Setting Register (Caulvr)
RX13T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.6 CAC Upper-Limit Value Setting Register (CAULVR) Address(es): 0008 B006h Value after reset: CAULVR is a 16-bit readable/writable register that specifies the upper-limit value of the counter used for measuring the frequency.
Page 164: Operation
RX13T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.3 Operation 10.3.1 Measuring Clock Frequency The clock frequency accuracy measurement circuit measures the clock frequency using the CACREF pin input or the internal clock as a reference. Figure 10.2 shows an operating example of the clock frequency accuracy measurement circuit.
Page 165: Digital Filtering Of Signals On The Cacref Pin
RX13T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. Also, the MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt is generated. (5) When the next valid edge is input, the counter value is transferred in CACNTBR and compared with the values of CAULVR and CALLVR.
Page 166: Usage Notes
RX13T Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.5 Usage Notes 10.5.1 Module Stop Function Setting CAC operation can be disabled or enabled using module stop control register C (MSTPCRC). The initial setting is for the CAC to be halted. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 167: Low Power Consumption
RX13T Group 11. Low Power Consumption Low Power Consumption 11.1 Overview This MCU has several functions for reducing power consumption, by setting clock dividers, stopping modules, changing to low power consumption mode in normal operation, and changing to operating power control mode. Table 11.1 lists the specifications of low power consumption functions, and Table 11.2 lists the conditions to change to low power consumption modes, states of the CPU and peripheral modules, and the method for exiting each mode.
Page 168 RX13T Group 11. Low Power Consumption Table 11.2 Operating Conditions of Each Power Consumption Mode Sleep Mode Deep Sleep Mode Software Standby Mode Entry trigger Control register + instruction Control register + instruction Control register + instruction Exit trigger Interrupt Interrupt Interrupt* After exiting from each mode, CPU...
Page 169 RX13T Group 11. Low Power Consumption Reset state Normal operation mode (Program execution state) WAIT instruction* WAIT instruction* WAIT instruction* SSBY = 0 All interrupts Interrupt* All interrupts MSTPCRA.MSTPA28 = 1 SSBY = 1 SSBY = 0 MSTPCRC.DSLPE = 1 Software standby Sleep mode Deep sleep mode...
Page 170 RX13T Group 11. Low Power Consumption Reset state Software Software Deep sleep mode Deep sleep mode standby mode standby mode Exit the reset state High-speed Middle-speed Sleep mode Sleep mode operating mode operating mode Set the OPCCR register : WAIT instruction : Interrupt Figure 11.2 Operating Modes...
Page 171: Register Descriptions
RX13T Group 11. Low Power Consumption 11.2 Register Descriptions 11.2.1 Standby Control Register (SBYCR) Address(es): 0008 000Ch SSBY — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b14 to b0 —...
Page 172: Module Stop Control Register A (Mstpcra)
RX13T Group 11. Low Power Consumption 11.2.2 Module Stop Control Register A (MSTPCRA) Address(es): 0008 0010h MSTPA MSTPA MSTPA — — — — — — — — — — — — — Value after reset: MSTPA MSTPA — — — —...
Page 173: Module Stop Control Register B (Mstpcrb)
RX13T Group 11. Low Power Consumption 11.2.3 Module Stop Control Register B (MSTPCRB) Address(es): 0008 0014h MSTPB MSTPB MSTPB MSTPB — — — — — — — — — — — — Value after reset: MSTPB MSTPB MSTPB — — —...
Page 174: Module Stop Control Register C (Mstpcrc)
RX13T Group 11. Low Power Consumption 11.2.4 Module Stop Control Register C (MSTPCRC) Address(es): 0008 0018h MSTPC DSLPE — — — — — — — — — — — — — — Value after reset: MSTPC — — — — —...
Page 175: Operating Power Control Register (Opccr)
RX13T Group 11. Low Power Consumption 11.2.5 Operating Power Control Register (OPCCR) Address(es): 0008 00A0h OPCM — — — — OPCM[2:0] Value after reset: Symbol Bit Name Description b2 to b0 OPCM[2:0] Operating Power Control 0 0 0: High-speed operating mode Mode Select 0 1 0: Middle-speed operating mode Settings other than above are prohibited.
Page 176 RX13T Group 11. Low Power Consumption Table 11.3 Operating Frequency and Voltage Ranges in Operating Power Control Modes Operating Frequency Range Flash Memory Programming/ Operating Flash Memory Read Frequency Erasure Frequency Operating Power OPCM Voltage Control Mode [2:0] Bits Range ICLK FCLK PCLKD...
Page 177: Reducing Power Consumption By Switching Clock Signals
RX13T Group 11. Low Power Consumption 11.3 Reducing Power Consumption by Switching Clock Signals The clock frequency can change by setting the SCKCR.FCK[3:0], ICK[3:0], PCKB[3:0], and PCKD[3:0] bits. The CPU, DTC, ROM, and RAM clocks can be set by the ICK[3:0] bits. The peripheral module clocks can be set by the PCKB[3:0] and PCKD[3:0] bits.
Page 178: Function For Lower Operating Power Consumption
RX13T Group 11. Low Power Consumption 11.5 Function for Lower Operating Power Consumption By selecting an appropriate operating power control mode according to the operating frequency and operating voltage, power consumption can be reduced in normal mode, sleep mode, and deep sleep mode. 11.5.1 Setting Operating Power Control Mode Examples of the procedures for switching operating power control modes are shown below:...
Page 179: Low Power Consumption Modes
RX13T Group 11. Low Power Consumption 11.6 Low Power Consumption Modes 11.6.1 Sleep Mode 11.6.1.1 Entry to Sleep Mode When the WAIT instruction is executed while the SBYCR.SSBY bit is 0, the CPU enters sleep mode. In sleep mode, the CPU stops operating but the contents of its internal registers are retained.
Page 180: Exit From Sleep Mode
RX13T Group 11. Low Power Consumption 11.6.1.2 Exit from Sleep Mode Exit from sleep mode is initiated by any interrupt, a RES# pin reset, a power-on reset, a voltage monitoring reset, or a reset caused by an IWDT underflow.  Initiated by an interrupt An interrupt initiates exit from sleep mode and the interrupt exception handling starts.
Page 181: Deep Sleep Mode
RX13T Group 11. Low Power Consumption 11.6.2 Deep Sleep Mode 11.6.2.1 Entry to Deep Sleep Mode When a WAIT instruction is executed with the MSTPCRC.DSLPE bit set to 1, the MSTPCRA.MSTPA28 bit set to 1, and the SBYCR.SSBY bit cleared to 0, a transition to deep sleep mode is made. * In deep sleep mode, the CPU and the DTC, ROM, and RAM clocks stop.
Page 182: Exit From Deep Sleep Mode
RX13T Group 11. Low Power Consumption 11.6.2.2 Exit from Deep Sleep Mode Exit from deep sleep mode is initiated by any interrupt, a RES# pin reset, a power-on reset, a voltage monitoring reset, or a reset caused by an IWDT underflow. ...
Page 183: Software Standby Mode
RX13T Group 11. Low Power Consumption 11.6.3 Software Standby Mode 11.6.3.1 Entry to Software Standby Mode When a WAIT instruction is executed with the SBYCR.SSBY bit set to 1, a transition to software standby mode is made. In this mode, the CPU, on-chip peripheral functions stop. However, the contents of the CPU internal registers, RAM data, the states of on-chip peripheral functions, the I/O ports are retained.
Page 184: Exit From Software Standby Mode
RX13T Group 11. Low Power Consumption 11.6.3.2 Exit from Software Standby Mode Exit from software standby mode is initiated by an external pin interrupt (the NMI or IRQ0 to IRQ5), peripheral function interrupts (the IWDT, and voltage monitoring), a RES# pin reset, a power-on reset, a voltage monitoring reset, or an independent watchdog timer reset.
Page 185: Example Of Software Standby Mode Application
RX13T Group 11. Low Power Consumption 11.6.3.3 Example of Software Standby Mode Application Figure 11.3 shows an example of entry to software standby mode by the falling edge of the IRQn pin, and exit from software standby mode by the rising edge of the IRQn pin. In this example, an IRQn interrupt is accepted with the IRQCRi.IRQMD[1:0] bits of the ICU set to 01b (falling edge), and then the IRQCRi.IRQMD[1:0] bits are set to 10b (rising edge).
Page 186: Usage Notes
RX13T Group 11. Low Power Consumption 11.7 Usage Notes 11.7.1 I/O Port States I/O port states are retained in software standby mode. Therefore, the supply current is not reduced if output signals are high level. 11.7.2 Module Stop State of DTC Before setting the MSTPCRA.MSTPA28 bit to 1, set the DTCST.DTCST bit of the DTC to 0 to avoid activating the DTC.
Page 187: Register Write Protection Function
RX13T Group 12. Register Write Protection Function Register Write Protection Function The register write protection function protects important registers from being overwritten for in case a program runs out of control. The registers to be protected are set with the protect register (PRCR). Table 12.1 lists the association between the PRCR bits and the registers to be protected.
Page 188: Register Descriptions
RX13T Group 12. Register Write Protection Function 12.1 Register Descriptions 12.1.1 Protect Register (PRCR) Address(es): 0008 03FEh PRKEY[7:0] — — — — PRC3 — PRC1 PRC0 Value after reset: Symbol Bit Name Description PRC0 Protect Bit 0 Enables writing to the registers related to the clock generation circuit. 0: Write disabled 1: Write enabled PRC1...
Page 189: Exception Handling
RX13T Group 13. Exception Handling Exception Handling 13.1 Exception Events During execution of a program by the CPU, the occurrence of a certain event may cause execution of that program to be suspended and execution of another program to be started. Such kinds of events are called exception events. The RX CPU supports seven types of exceptions.
Page 190: Undefined Instruction Exception
RX13T Group 13. Exception Handling 13.1.1 Undefined Instruction Exception An undefined instruction exception occurs when execution of an undefined instruction (an instruction not implemented) is detected. 13.1.2 Privileged Instruction Exception A privileged instruction exception occurs when execution of a privileged instruction is detected in user mode. Privileged instructions can be executed only in supervisor mode.
Page 191: Exception Handling Procedure
RX13T Group 13. Exception Handling 13.2 Exception Handling Procedure In the exception handling, part of the processing is handled automatically by hardware and part of it is handled by a program (exception handling routine) that has been written by the user. Figure 13.2 shows the processing procedure when an exception other than a reset is accepted.
Page 192 RX13T Group 13. Exception Handling When an exception is accepted, hardware processing by the RX CPU is followed by access to the vector to acquire the address of the branch destination. In the vector, a vector address is allocated to each exception, and the branch destination address of the exception handling routine is written to each vector address.
Page 193: Acceptance Of Exception Events
RX13T Group 13. Exception Handling 13.3 Acceptance of Exception Events When an exception occurs, the CPU suspends the execution of the program and processing branches to the exception handling routine. 13.3.1 Acceptance Timing and Saved PC Value Table 13.1 lists the timing of acceptance and the program counter (PC) value to be saved for each exception event. Table 13.1 Acceptance Timing and Saved PC Value Acceptance...
Page 194: Hardware Processing For Accepting And Returning From Exceptions
RX13T Group 13. Exception Handling 13.4 Hardware Processing for Accepting and Returning from Exceptions This section describes the hardware processing for accepting and returning from exceptions other than a reset. (1) Hardware Pre-Processing for Accepting an Exception (a) Saving PSW ...
Page 195: Hardware Pre-Processing
RX13T Group 13. Exception Handling 13.5 Hardware Pre-Processing The hardware pre-processing from reception of each exception request to execution of the associated exception handling routine are explained below. 13.5.1 Undefined Instruction Exception 1. The value of the processor status word (PSW) is saved on the stack (ISP). 2.
Page 196: Interrupt
RX13T Group 13. Exception Handling 13.5.6 Interrupt 1. The value of the processor status word (PSW) is saved on the stack (ISP) or, for the fast interrupt, in the backup PSW (BPSW). 2. The processor mode select bit (PM), the stack pointer select bit (U), and the interrupt enable bit (I) in PSW are set to 3.
Page 197: Return From Exception Handling Routine
RX13T Group 13. Exception Handling 13.6 Return from Exception Handling Routine Executing the instruction listed in Table 13.3 at the end of the corresponding exception handling routine restores the values of the program counter (PC) and processor status word (PSW) that were saved on the stack or in the control registers (BPC and BPSW) immediately before the exception handling sequence.
Page 198: Interrupt Controller (Icub)
RX13T Group 14. Interrupt Controller (ICUb) Interrupt Controller (ICUb) 14.1 Overview The interrupt controller receives interrupt requests from peripheral modules and external pins, and generates an interrupt request to the CPU and a transfer request to the DTC. Table 14.1 lists the specifications of the interrupt controller, and Figure 14.1 shows a block diagram of the interrupt controller.
Page 199 RX13T Group 14. Interrupt Controller (ICUb) Interrupt controller Voltage monitoring 2 interrupt Clock Voltage monitoring 1 interrupt generation Clock restoration request IWDT underflow/refresh error circuit Clock Oscillation stop detection interrupt restoration NMI pin Digital filter Detection judgment Clock restoration enable level Non-maskable interrupt request IFLTE IFLTC...
Page 200: Register Descriptions
RX13T Group 14. Interrupt Controller (ICUb) 14.2 Register Descriptions 14.2.1 Interrupt Request Register n (IRn) (n = interrupt vector number) Address(es): ICU.IR016 0008 7010h to ICU.IR255 0008 70FFh — — — — — — — Value after reset: Symbol Bit Name Description Interrupt Status Flag 0: No interrupt request is generated...
Page 201: Interrupt Request Enable Register M (Ierm) (M = 02H To 1Fh)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.2 Interrupt Request Enable Register m (IERm) (m = 02h to 1Fh) Address(es): ICU.IER02 0008 7202h to ICU.IER1F 0008 721Fh IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Value after reset: Symbol Bit Name Description IEN0 Interrupt Request Enable 0...
Page 202: Interrupt Source Priority Register N (Iprn) (N = Interrupt Vector Number)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.3 Interrupt Source Priority Register n (IPRn) (n = interrupt vector number) Address(es): ICU.IPR000 0008 7300h to ICU.IPR255 0008 73FFh — — — — IPR[3:0] Value after reset: Symbol Bit Name Description b3 to b0 IPR[3:0] Interrupt Priority Level Select 0 0 0 0: Level 0 (interrupt disabled)*...
Page 203: Fast Interrupt Set Register (Fir)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.4 Fast Interrupt Set Register (FIR) Address(es): ICU.FIR 0008 72F0h FIEN — — — — — — — FVCT[7:0] Value after reset: Symbol Bit Name Description b7 to b0 FVCT[7:0] Fast Interrupt Vector Number Specify the vector number of an interrupt source to be a fast interrupt.
Page 204: Software Interrupt Generation Register (Swintr)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.5 Software Interrupt Generation Register (SWINTR) Address(es): ICU.SWINTR 0008 72E0h — — — — — — — SWINT Value after reset: Symbol Bit Name Description SWINT Software Interrupt Generation This bit is read as 0. Writing 1 issues a software interrupt request. R/(W) Writing 0 to this bit has no effect.
Page 205: Dtc Transfer Request Enable Register N (Dtcern) (N = Interrupt Vector Number)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.6 DTC Transfer Request Enable Register n (DTCERn) (n = interrupt vector number) Address(es): ICU.DTCER027 0008 711Bh to ICU.DTCER255 0008 71FFh — — — — — — — DTCE Value after reset: Symbol Bit Name Description DTCE DTC Transfer Request...
Page 206: Irq Control Register I (Irqcri) (I = 0 To 5)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.7 IRQ Control Register i (IRQCRi) (i = 0 to 5) Address(es): ICU.IRQCR0 0008 7500h to ICU.IRQCR5 0008 7505h — — — — IRQMD[1:0] — — Value after reset: Symbol Bit Name Description b1, b0 —...
Page 207: Irq Pin Digital Filter Enable Register 0 (Irqflte0)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.8 IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) Address(es): ICU.IRQFLTE0 0008 7510h FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN — — Value after reset: Symbol Bit Name Description FLTEN0 IRQ0 Digital Filter Enable 0: Digital filter is disabled 1: Digital filter is enabled FLTEN1 IRQ1 Digital Filter Enable...
Page 208: Irq Pin Digital Filter Setting Register 0 (Irqfltc0)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.9 IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) Address(es): ICU.IRQFLTC0 0008 7514h — — — — FCLKSEL5[1:0] FCLKSEL4[1:0] FCLKSEL3[1:0] FCLKSEL2[1:0] FCLKSEL1[1:0] FCLKSEL0[1:0] Value after reset: Symbol Bit Name Description b1, b0 FCLKSEL0[1:0] IRQ0 Digital Filter Sampling Clock 0 0: PCLK 0 1: PCLK/8 b3, b2...
Page 209: Non-Maskable Interrupt Status Register (Nmisr)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.10 Non-Maskable Interrupt Status Register (NMISR) Address(es): ICU.NMISR 0008 7580h LVD2S LVD1S IWDTS — — — OSTST NMIST Value after reset: Symbol Bit Name Description NMIST NMI Status Flag 0: NMI pin interrupt is not requested 1: NMI pin interrupt is requested OSTST Oscillation Stop Detection...
Page 210 RX13T Group 14. Interrupt Controller (ICUb)  When the IWDT underflow/refresh error interrupt is generated while this interrupt is enabled at its source. [Clearing condition]  When 1 is written to the NMICLR.IWDTCLR bit LVD1ST Flag (Voltage Monitoring 1 Interrupt Status Flag) This flag indicates the request for voltage monitoring 1 interrupt.
Page 211: Non-Maskable Interrupt Enable Register (Nmier)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.11 Non-Maskable Interrupt Enable Register (NMIER) Address(es): ICU.NMIER 0008 7581h LVD2E LVD1E IWDTE — — — OSTEN NMIEN Value after reset: Symbol Bit Name Description NMIEN NMI Pin Interrupt Enable 0: NMI pin interrupt is disabled R/(W) 1: NMI pin interrupt is enabled OSTEN...
Page 212: Non-Maskable Interrupt Status Clear Register (Nmiclr)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.12 Non-Maskable Interrupt Status Clear Register (NMICLR) Address(es): ICU.NMICLR 0008 7582h LVD2C LVD1C IWDTC OSTCL NMICL — — — Value after reset: Symbol Bit Name Description NMICLR NMI Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.NMIST flag. R/(W) Writing 0 to this bit has no effect.
Page 213: Nmi Pin Interrupt Control Register (Nmicr)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.13 NMI Pin Interrupt Control Register (NMICR) Address(es): ICU.NMICR 0008 7583h — — — — NMIMD — — — Value after reset: Symbol Bit Name Description b2 to b0 — Reserved These bits are read as 0. The write value should be 0. NMIMD NMI Detection Set 0: Falling edge...
Page 214: Nmi Pin Digital Filter Setting Register (Nmifltc)
RX13T Group 14. Interrupt Controller (ICUb) 14.2.15 NMI Pin Digital Filter Setting Register (NMIFLTC) Address(es): ICU.NMIFLTC 0008 7594h — — — — — — NFCLKSEL[1:0] Value after reset: Symbol Bit Name Description b1, b0 NFCLKSEL[1:0] NMI Digital Filter Sampling b1 b0 0 0: PCLK Clock 0 1: PCLK/8...
Page 215: Vector Table
RX13T Group 14. Interrupt Controller (ICUb) 14.3 Vector Table There are two types of interrupts detected by the interrupt controller: maskable interrupts and non-maskable interrupts. When the CPU accepts an interrupt or non-maskable interrupt, it acquires a 4-byte vector address from the vector table. 14.3.1 Interrupt Vector Table The interrupt vector table is placed in the 1024-byte range (4 bytes ×...
Page 216 RX13T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (1/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — For an unconditional trap 0000h — — — — — For an unconditional trap 0004h —...
Page 217 RX13T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (2/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — Reserved 00C8h ― — — — — Reserved 00CCh ― — —...
Page 218 RX13T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (3/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — Reserved 0194h ― — — — S12AD S12ADI 0198h Edge IER0C.IEN6 IPR102 DTCER102 ...
Page 219 RX13T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (4/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — Reserved 0260h ― — — — — Reserved 0264h ― — —...
Page 220 RX13T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (5/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — Reserved 032Ch ― — — — — Reserved 0330h ― — —...
Page 221: Fast Interrupt Vector Table
RX13T Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (6/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — Reserved 03F8h ― — — — — Reserved 03FCh ― — —...
Page 222: Interrupt Operation
RX13T Group 14. Interrupt Controller (ICUb) 14.4 Interrupt Operation The interrupt controller performs the following processing.  Detecting interrupts  Enabling and disabling interrupts  Selecting interrupt request destinations (CPU interrupt or DTC trigger)  Determining priority 14.4.1 Detecting Interrupts Interrupt requests are detected in either of two ways: the detection of edges of the interrupt signal or the detection of a level of the interrupt signal.
Page 223 RX13T Group 14. Interrupt Controller (ICUb) Figure 14.3 to Figure 14.5 show the interrupt signals of the interrupt controller. Note that the timings of the interrupts with interrupt vector numbers 64 to 95 are different from those of other interrupts. For the IRQ pin interrupts with interrupt vector numbers 64 to 79, “internal delay + 2 PCLK cycles”...
Page 224: Operation Of Status Flags For Level-Detected Interrupts
RX13T Group 14. Interrupt Controller (ICUb) 14.4.1.2 Operation of Status Flags for Level-Detected Interrupts Figure 14.5 shows the operation of the interrupt status flag (IR flag) in IRn (n = interrupt vector number) in the case of level detection of an interrupt from a peripheral module or an external pin. The IR flag in IRn remains set to 1 as long as the interrupt signal is asserted.
Page 225: Enabling And Disabling Interrupt Sources
RX13T Group 14. Interrupt Controller (ICUb) 14.4.2 Enabling and Disabling Interrupt Sources Enabling requests from a given interrupt source requires the following settings. 1. In the case of interrupt requests from peripheral modules, setting the interrupt enable bit for the peripheral module to permit the output of interrupt requests from the source 2.
Page 226: Selecting Interrupt Request Destinations
RX13T Group 14. Interrupt Controller (ICUb) 14.4.3 Selecting Interrupt Request Destinations Possible settings for the request destination of each interrupt are fixed. That is, settings for request destination other than those indicated in Table 14.3, Interrupt Vector Table , are not possible. Do not make an interrupt request destination setting that is not indicated by a “”...
Page 227: Determining Priority
RX13T Group 14. Interrupt Controller (ICUb) 14.4.4 Determining Priority Interrupt priority is determined for each interrupt request destination. The priority for each interrupt request destination is determined as follows. (1) Determining Priority when the CPU is the Request Destination of the Interrupt A source selected for the fast interrupt has the highest priority.
Page 228: Digital Filter
RX13T Group 14. Interrupt Controller (ICUb) 14.4.7 Digital Filter The digital filter function is provided for the external interrupt request IRQi pins (i = 0 to 5) and NMI pin interrupt. The digital filter samples input signals at the filter sampling clock (PCLK) and removes the pulses of which length is less than three sampling cycles.
Page 229: Non-Maskable Interrupt Operation
RX13T Group 14. Interrupt Controller (ICUb) 14.5 Non-maskable Interrupt Operation There are six types of non-maskable interrupt: the NMI pin interrupt, oscillation stop detection interrupt, IWDT underflow/refresh error, voltage monitoring 1 interrupt, and voltage monitoring 2 interrupt. Non-maskable interrupts are only usable as interrupts for the CPU;...
Page 230: Return From Power-Down States
RX13T Group 14. Interrupt Controller (ICUb) 14.6 Return from Power-Down States The interrupt sources that can be used to return operation from sleep mode, deep sleep mode, or software standby mode are listed in Table 14.3, Interrupt Vector Table . For details, refer to section 11, Low Power Consumption .
Page 231: Usage Note
RX13T Group 14. Interrupt Controller (ICUb) 14.7 Usage Note 14.7.1 Note on WAIT Instruction Used with Non-Maskable Interrupt Before executing the WAIT instruction, check to see that all the status flags in NMISR are 0. R01UH0822EJ0100 Rev.1.00 Page 231 of 1041 Jul 31, 2019...
Page 232: Buses
RX13T Group 15. Buses Buses 15.1 Overview Table 15.1 lists the bus specifications, Figure 15.1 shows the bus configuration, and Table 15.2 lists the addresses assigned to each bus. Table 15.1 Bus Specifications Bus Type Description  Connected to the CPU for instructions CPU bus Instruction bus ...
Page 233 RX13T Group 15. Buses ICLK synchronization Instruction bus Operand bus Memory Memory Bus error bus 1 bus 2 monitoring section DTC (m) Internal main bus 1 Internal main bus 2 Internal Internal peripheral peripheral bus 1 Internal buses 2 and 3 peripheral bus 6 Peripheral DTC (s)
Page 234: Description Of Buses
RX13T Group 15. Buses 15.2 Description of Buses 15.2.1 CPU Buses The CPU buses consist of the instruction and operand buses, which are connected to internal main bus 1. As the names suggest, the instruction bus is used to fetch instructions for the CPU, while the operand bus is used for operand access. Connection of the instruction and operand buses to RAM and ROM provides the CPU with direct access to these areas, i.e.
Page 235: Internal Peripheral Buses
RX13T Group 15. Buses 15.2.4 Internal Peripheral Buses Connection of peripheral modules to the internal peripheral buses is as described in Table 15.4 . Table 15.4 Connection of Peripheral Modules to the Internal Peripheral Buses Type of Bus Peripheral Modules Internal peripheral bus 1 DTC, interrupt controller, and bus error monitoring section Internal peripheral bus 2...
Page 236: Write Buffer Function (Internal Peripheral Bus)
RX13T Group 15. Buses 15.2.5 Write Buffer Function (Internal Peripheral Bus) The internal peripheral bus has the write buffer function, which allows the next round of bus access to start, before the current write access is completed, in write access. However, if the following round of bus access is from the same bus master but to the different internal peripheral bus, it is suspended until the bus operations already in progress are completed.
Page 237: Parallel Operation
RX13T Group 15. Buses 15.2.6 Parallel Operation Parallel operation is possible when different bus-master modules are requesting access to different slave modules. For example, if the CPU is fetching an instruction from ROM and an operand from RAM, the DTC is able to handle transfer between a peripheral bus and peripheral bus at the same time.
Page 238: Register Descriptions
RX13T Group 15. Buses 15.3 Register Descriptions 15.3.1 Bus Error Status Clear Register (BERCLR) Address(es): 0008 1300h STSCL — — — — — — — Value after reset: Symbol Bit Name Description STSCLR Status Clear 0: Invalid (W)* 1: Bus error status register cleared b7 to b1 —...
Page 239: Bus Error Status Register 1 (Bersr1)
RX13T Group 15. Buses 15.3.3 Bus Error Status Register 1 (BERSR1) Address(es): 0008 1308h — MST[2:0] — — Value after reset: Symbol Bit Name Description Illegal Address Access 0: Illegal address access not made 1: Illegal address access made Timeout 0: Timeout not generated 1: Timeout generated b3, b2...
Page 240: Bus Priority Control Register (Buspri)
RX13T Group 15. Buses 15.3.5 Bus Priority Control Register (BUSPRI) Address(es): 0008 1310h — — — — BPFB[1:0] — — BPGB[1:0] BPIB[1:0] BPRO[1:0] BPRA[1:0] Value after reset: Symbol Bit Name Description b1, b0 BPRA[1:0] Memory Bus 1 (RAM) Priority R/(W) b1 b0 0 0: The order of priority is fixed.
Page 241 RX13T Group 15. Buses BPGB[1:0] Bits (Internal Peripheral Buses 2 and 3 Priority Control) These bits specify the priority order for internal peripheral buses 2 and 3. When the priority order is fixed, internal main bus 2 has priority over internal main bus 1. When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
Page 242: Bus Error Monitoring Section
RX13T Group 15. Buses 15.4 Bus Error Monitoring Section The bus error monitoring section monitors the individual areas for bus errors, and when a bus error occurs, the error is indicated to the bus master. 15.4.1 Type of Bus Error There are two types of bus error: illegal address access and timeout.
Page 243: Conditions Leading To Bus Errors
RX13T Group 15. Buses 15.4.3 Conditions Leading to Bus Errors Table 15.5 lists the type of bus errors for each area in the respective address space. If an illegal address access error or timeout is detected when no bus error has occurred (bus error status register n (BERSRn;...
Page 244: Interrupt
RX13T Group 15. Buses 15.5 Interrupt 15.5.1 Interrupt Source An illegal address access error or detection of a timeout leads to a bus error signal for the interrupt controller. Table 15.6 Interrupt Source Name Interrupt Source DTC Activation BUSERR Illegal address access error or timeout Not possible R01UH0822EJ0100 Rev.1.00 Page 244 of 1041...
Page 245: Data Transfer Controller (Dtcb)
RX13T Group 16. Data Transfer Controller (DTCb) Data Transfer Controller (DTCb) This MCU incorporates a data transfer controller (DTC). The DTC is triggered by an interrupt request to perform data transfers. In addition to the conventional methods of DTC transfer (normal, repeat, block, and chain), DTCb supports sequential transfer, in which it handles a series of transfers made up of a combination of the other methods.
Page 246 RX13T Group 16. Data Transfer Controller (DTCb) Register Vector number control Interrupt controller Activation Transfer request control DTC response Bus interface DTCCR DTCVBR response control DTCADMOD DTCST DTCSTS DTCIBR DTCOR DTCSQE DTCDISP Internal peripheral bus 1 Internal main bus 2 Internal main bus 1 Internal Memory bus 2...
Page 247: Register Descriptions
RX13T Group 16. Data Transfer Controller (DTCb) 16.2 Register Descriptions Registers MRA, MRB, MRC, SAR, DAR, CRA, and CRB are DTC internal registers, which cannot be directly accessed from the CPU. Values to be set in these DTC internal registers are placed in the RAM area as transfer information. When accepting a transfer request, the DTC reads the transfer information from the RAM area and sets it in the internal registers.
Page 248 RX13T Group 16. Data Transfer Controller (DTCb) (1) Normal transfer and repeat transfer modes 1-byte, 1-word, or 1-longword of data is transferred on a single transfer request. The transfer address and transfer count are not updated so that the same transfer is repeated on each transfer request. When the transfer count is 1, the ICU.DTCERn.DTCE bit is not set to 0, and data transfer continues in response to the next transfer request.
Page 249: Dtc Mode Register B (Mrb)
RX13T Group 16. Data Transfer Controller (DTCb) 16.2.2 DTC Mode Register B (MRB) Address(es): (inaccessible directly from the CPU) CHNE CHNS DISEL DM[1:0] INDX SQEND Value after reset: x: Undefined Symbol Bit Name Description SQEND Sequence Transfer End 0: Continue the sequence transfer —...
Page 250 RX13T Group 16. Data Transfer Controller (DTCb) Table 16.2 Values of Bits CHNE, SQEND, and INDX in the Sequence Transfer and DTC Operation CHNE Bit SQEND Bit INDX Bit Operation Usage Start sequence transfer Use this setting for the transfer information that is first read in response to a transfer request from the source specified in the DTCSQE register.
Page 251: Dtc Mode Register C (Mrc)
RX13T Group 16. Data Transfer Controller (DTCb) 16.2.3 DTC Mode Register C (MRC) Address(es): (inaccessible directly from the CPU) — — — — — — — DISPE Value after reset: x: Undefined Symbol Bit Name Description DISPE Displacement Addition 0: The displacement value is not added to the transfer source —...
Page 252: Dtc Transfer Source Register (Sar)
RX13T Group 16. Data Transfer Controller (DTCb) 16.2.4 DTC Transfer Source Register (SAR) Address(es): (inaccessible directly from the CPU) Value after reset: Value after reset: x: Undefined SAR register is used to set the transfer source start address. In full-address mode, 32 bits are valid. In short-address mode, lower 24 bits are valid and upper 8 bits (b31 to b24) are ignored.
Page 253: Dtc Transfer Count Register A (Cra)
RX13T Group 16. Data Transfer Controller (DTCb) 16.2.6 DTC Transfer Count Register A (CRA)  Normal transfer mode Address(es): (inaccessible directly from the CPU) Value after reset: x: Undefined  Repeat transfer mode/block transfer mode Address(es): (inaccessible directly from the CPU) CRAH CRAL Value after reset:...
Page 254: Dtc Transfer Count Register B (Crb)
RX13T Group 16. Data Transfer Controller (DTCb) 16.2.7 DTC Transfer Count Register B (CRB) Address(es): (inaccessible directly from the CPU) Value after reset: x: Undefined CRB register is used to set the block transfer count for block transfer mode and cannot be accessed directly from the CPU.
Page 255: Dtc Vector Base Register (Dtcvbr)
RX13T Group 16. Data Transfer Controller (DTCb) 16.2.9 DTC Vector Base Register (DTCVBR) Address(es): DTC.DTCVBR 0008 2404h Value after reset: Value after reset: The DTCVBR register is used to set the base address for calculating the address to which the DTC vector is allocated. Writing to the upper 4 bits (b31 to b28) is ignored, and the address of this register is extended by the value specified by b27.
Page 256: Dtc Module Start Register (Dtcst)
RX13T Group 16. Data Transfer Controller (DTCb) 16.2.11 DTC Module Start Register (DTCST) Address(es): DTC.DTCST 0008 240Ch — — — — — — — DTCST Value after reset: Symbol Bit Name Description DTCST DTC Module Start 0: DTC module stop 1: DTC module start b7 to b1 —...
Page 257: Dtc Status Register (Dtcsts)
RX13T Group 16. Data Transfer Controller (DTCb) 16.2.12 DTC Status Register (DTCSTS) Address(es): DTC.DTCSTS 0008 240Eh — — — — — — — VECN[7:0] Value after reset: Symbol Bit Name Description b7 to b0 VECN[7:0] DTC Active Vector Number These bits indicate the vector number for the request source when Monitoring Flag data transfer is in progress.
Page 258: Dtc Index Table Base Register (Dtcibr)
RX13T Group 16. Data Transfer Controller (DTCb) 16.2.13 DTC Index Table Base Register (DTCIBR) Address(es): DTC.DTCIBR 0008 2410h Value after reset: Value after reset: The DTCIBR register is used to set the base address for calculating the address to which the DTC index is allocated. Writing to the upper 4 bits (b31 to b28) is ignored, and the address of this register is extended by the value specified by b27.
Page 259: Dtc Operation Register (Dtcor)
RX13T Group 16. Data Transfer Controller (DTCb) 16.2.14 DTC Operation Register (DTCOR) Address(es): DTC.DTCOR 0008 2414h SQTFR — — — — — — — Value after reset: Symbol Bit Name Description SQTFRL Sequence Transfer Terminate Writing 1 to this bit terminates the sequence transfer in progress.
Page 260: Dtc Sequence Transfer Enable Register (Dtcsqe)
RX13T Group 16. Data Transfer Controller (DTCb) 16.2.15 DTC Sequence Transfer Enable Register (DTCSQE) Address(es): DTC.DTCSQE 0008 2416h ESPSE — — — — — — — VECN[7:0] Value after reset: Symbol Bit Name Description b7 to b0 VECN[7:0] Sequence Transfer Vector Specify the vector number by which a sequence transfer is Number Setting enabled.
Page 261: Request Sources
RX13T Group 16. Data Transfer Controller (DTCb) 16.3 Request Sources The DTC data transfer is triggered by an interrupt request. Setting the ICU.DTCERn.DTCE bit (n = interrupt vector number) to 1 selects the corresponding interrupt request as a request source for the DTC. For the correspondence between the DTC request sources and the vector addresses, refer to section 14.3.1, Interrupt Vector Table in section 14, Interrupt Controller (ICUb) .
Page 262 RX13T Group 16. Data Transfer Controller (DTCb) DTC vector table Transfer information 0 DTC vector base address Start address of transfer information 0 Start address of transfer information 1 Start address of Transfer information 1 transfer information 2 Start address of transfer information n 4 bytes Transfer information n...
Page 263: Operation
RX13T Group 16. Data Transfer Controller (DTCb) 16.4 Operation The DTC transfers data in accordance with the transfer information. Storage of the transfer information in the RAM area is required before DTC operation. When the DTC accepts a transfer request, it reads the DTC vector corresponding to the vector number. Next, the DTC reads transfer information from the address pointed by the DTC vector, transfers data, and then writes back the transfer information after the data transfer.
Page 264 RX13T Group 16. Data Transfer Controller (DTCb) Start Match and RRS bit = 1 Compare vector numbers. Match? Unmatch or RRS bit = 0 Read DTC vector Next transfer Read transfer information CHNE bit = 1? MD[1:0] bits = 01b? CHNS bit = 0? (Repeat transfer mode?) WBDIS = 0 and...
Page 265: Transfer Information Read Skip Function
RX13T Group 16. Data Transfer Controller (DTCb) Table 16.4 Chain Transfer Conditions First Transfer Second Transfer* CHNE CHNS DISEL Transfer CHNE CHNS DISEL Transfer Counter* Counter* Data Transfer — Other than (1 → 0) — — — — Ends after the first transfer —...
Page 266: Transfer Information Write-Back Skip Function
RX13T Group 16. Data Transfer Controller (DTCb) 16.4.2 Transfer Information Write-Back Skip Function 16.4.2.1 Write-Back Skip by Fixing Addresses When the MRA.SM[1:0] bits or the MRB.DM[1:0] bits are set to “address is fixed” (00b or 01b), a part of transfer information is not written back.
Page 267: Normal Transfer Mode
RX13T Group 16. Data Transfer Controller (DTCb) 16.4.3 Normal Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single transfer request. The transfer count can be set to 1 to 65536. Transfer source addresses and transfer destination addresses can be set to increment, decrement, or fixed independently. This mode enables an interrupt request to the CPU to be generated at the end of specified-count transfer.
Page 268: Repeat Transfer Mode
RX13T Group 16. Data Transfer Controller (DTCb) 16.4.4 Repeat Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single transfer request. Specify either transfer source or transfer destination for the repeat area by the MRB.DTS bit. The transfer count can be set to 1 to 256.
Page 269: Block Transfer Mode
RX13T Group 16. Data Transfer Controller (DTCb) 16.4.5 Block Transfer Mode This mode allows single-block data transfer on a single transfer request. Specify either transfer source or transfer destination for the block area by the MRB.DTS bit. The block size can be set to 1 to 256 bytes, 1 to 256 words, or 1 to 256 longwords.
Page 270: Chain Transfer
RX13T Group 16. Data Transfer Controller (DTCb) 16.4.6 Chain Transfer Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single transfer request. If the MRB.CHNE bit is 1 and the MRB.CHNS bit is 0, an interrupt request to the CPU is not generated when the specified number of data transfers is completed, or while the MRB.DISEL bit is 1 (an interrupt request to the CPU is generated for every data transfer).
Page 271: Operation Timing
RX13T Group 16. Data Transfer Controller (DTCb) 16.4.7 Operation Timing Figure 16.10 to Figure 16.14 show examples of DTC operation timing. System clock ICU.IRn DTC transfer request DTC access Transfer Data Vector read Transfer information read transfer information write n = Vector number Figure 16.10 Example (1) of DTC Operation Timing (Short-Address Mode, Normal Transfer Mode, Repeat Transfer Mode)
Page 272 RX13T Group 16. Data Transfer Controller (DTCb) System clock ICU.IRn DTC transfer request DTC access Data Data Transfer Transfer Transfer Transfer Vector read transfer transfer information read information information information write read write n = Vector number Figure 16.12 Example (3) of DTC Operation Timing (Short-Address Mode, Chain Transfer) System clock ICU.IRn DTC transfer request...
Page 273 RX13T Group 16. Data Transfer Controller (DTCb) System clock ICU.IRn DTC transfer request Read skip enable DTC access Data Transfer Vector read Transfer Transfer Data transfer information write information read information write transfer n = Vector number Note: When request sources (vector numbers) of (1) and (2) are the same and the DTCCR.RRS bit is 1, the transfer information read for request (2) is skipped.
Page 274: Execution Cycles Of The Dtc
RX13T Group 16. Data Transfer Controller (DTCb) 16.4.8 Execution Cycles of the DTC Table 16.9 lists the execution cycles of single data transfer of the DTC. For the order of the execution states, refer to section 16.4.7, Operation Timing . Table 16.9 Execution Cycles of the DTC Data Transfer...
Page 275: Sequence Transfer
RX13T Group 16. Data Transfer Controller (DTCb) 16.4.10 Sequence Transfer A sequence transfer can be executed on the request source that is specified in the DTCSQE register. A sequence transfer is started by setting the MRB.INDX bit to 1 and ended by setting the MRB.SQEND bit to 1. Setting the DTCOR.SQTFRL bit to 1, even during a sequence transfer, forcibly ends the transfer and the next DTC transfer request starts new sequence transfer with reference to the index table.
Page 276 RX13T Group 16. Data Transfer Controller (DTCb) DTC vector table Transfer information Transfer information Start address of DTC vector address INDX = 1 Data transfer information (Start sequence transfer) DTCVBR + n × 4 Sequence number = p DTC index table Transfer information Transfer information DTC index address...
Page 277: Dtc Index Table
RX13T Group 16. Data Transfer Controller (DTCb) 16.4.11 DTC Index Table The DTC index table is allocated to the area where its start address is configured in the DTCIBR register. Store the start address of transfer information table p for sequence number p in the address of DTCIBR + p × 4. The upper 30 bits of the start address is set to the upper 30 bits of the DTC index.
Page 278 RX13T Group 16. Data Transfer Controller (DTCb)  DTC Index Address(es): DTCIBR + p × 4 DTCIADDR[31:16] Value after reset: CPUSE DTCIADDR[15:2] — Value after reset: Symbol Bit Name Description CPUSEL Sequence Transfer/CPU Interrupt 0: Continues the sequence transfer (starts the —...
Page 279: Example Of Sequence Transfer
RX13T Group 16. Data Transfer Controller (DTCb) 16.4.12 Example of Sequence Transfer Figure 16.18 shows a typical examples of a sequence transfer and Figure 16.19 to Figure 16.23 show configurations of the transfer information for the examples of the transfers in the figure. In these examples, the interrupt source of vector number n is set as the source of the sequence transfer (DTCSQE.VECN[7:0] = n).
Page 280 RX13T Group 16. Data Transfer Controller (DTCb) (1) When Executing a Single Transfer Figure 16.19 shows an example of a single transfer (normal, repeat, or block). The DTC refers to the DTC index table, and reads the transfer information corresponding to the obtained sequence number p.
Page 281 RX13T Group 16. Data Transfer Controller (DTCb) (2) When Executing a Single Chain Transfer Figure 16.20 is an example of a sequence for a single chain transfer. The DTC refers to the DTC index table, and reads the transfer information corresponding to the obtained sequence number q.
Page 282 RX13T Group 16. Data Transfer Controller (DTCb) (3) When Dividing a Sequence Figure 16.21 is an example of the sequence that is divided into 3 parts. The DTC refers to the DTC index table, and reads the transfer information corresponding to the obtained sequence number r.
Page 283 RX13T Group 16. Data Transfer Controller (DTCb) (4) When Starting a New Sequence on completion of a Sequence Figure 16.22 is an example for starting the next and new sequence on completion of the first sequence. The DTC refers to the DTC index table, and reads the transfer information corresponding to the obtained sequence number s.
Page 284 RX13T Group 16. Data Transfer Controller (DTCb) (5) When Generating an Interrupt Request to the CPU Figure 16.23 is an example of that an interrupt request is output to the CPU without starting of sequence. The DTC obtains a DTC index that corresponds to the obtained sequence number t. When the CPUSEL bit of the obtained DTC index is 1, the DTC ends the sequence transfer without starting the sequence, and then outputs an interrupt request to the CPU.
Page 285: Dtc Setting Procedure
RX13T Group 16. Data Transfer Controller (DTCb) 16.5 DTC Setting Procedure Before using the DTC, set the DTC vector base register (DTCVBR). When using sequence transfer, also set the DTC index table base register (DTCIBR). Figure 16.24 shows the procedure to set the DTC. Set the ICU.IERm.IENj bit corresponding to the request source interrupt to 0 and provide the following settings.
Page 286: Examples Of Dtc Usage
RX13T Group 16. Data Transfer Controller (DTCb) 16.6 Examples of DTC Usage 16.6.1 Normal Transfer As an example of DTC usage, its employment in the reception of 128 bytes of data by an SCI is described below. (1) Transfer Information Setting Set the MRA.MD[1:0] bits to 00b (normal transfer mode), the MRA.SZ[1:0] bits to 00b (byte transfer), and the MRA.SM[1:0] bits to 00b (source address is fixed).
Page 287: Chain Transfer When The Counter Is 0
RX13T Group 16. Data Transfer Controller (DTCb) 16.6.2 Chain Transfer When the Counter is 0 The second data transfer is performed only when the transfer counter is set to 0 in the first data transfer, and the first data transfer information is repeatedly changed in the second data transfer. Repeating this chain transfer enables transfers to be repeated more than 256 times.
Page 288: Sequence Transfer
RX13T Group 16. Data Transfer Controller (DTCb) Input circuit Transfer information allocated in the on-chip memory space Input buffer First data transfer Transfer information Chain transfer (counter = 0) Second data transfer Transfer information Upper 8 bits of DAR Figure 16.25 Chain Transfer When the Counter is 0 16.6.3 Sequence Transfer...
Page 289: Interrupt Source
RX13T Group 16. Data Transfer Controller (DTCb) (5) SCI Setting Set the SCIk.SCR.RIE bit to 1 to enable the RXI interrupt. If a reception error occurs during the SCI receive operation, subsequent receptions are not performed. Accordingly, make settings so that the CPU can accept receive error interrupts. (6) Start of the Sequence Transfer On completion of reception of 1-byte data by the SCI, an RXI interrupt is generated to start the DTC.
Page 290: Low Power Consumption Function
RX13T Group 16. Data Transfer Controller (DTCb) 16.8 Low Power Consumption Function Before making a transition to the module stop state, deep sleep mode, or software standby mode, set the DTCST.DTCST bit to 0 (DTC module stop), and then perform the following. (1) Module Stop Function Writing 1 (transition to the module-stop state is made) to the MSTPCRA.MSTPA28 bit enables the module stop function of the DTC.
Page 291: Usage Notes
RX13T Group 16. Data Transfer Controller (DTCb) 16.9 Usage Notes 16.9.1 Start Address of Transfer Information Set multiples of 4 for the start addresses of the transfer information to be specified in the DTC vector table. If any value other than a multiple of 4 is specified, access still proceeds with the lower 2 bits of the address regarded as 00b. 16.9.2 Allocating Transfer Information Allocate transfer information in the memory area according to the endian of the area as shown in Figure 16.26 .
Page 292: Notes On Using The Sequence Transfer
RX13T Group 16. Data Transfer Controller (DTCb) 16.9.3 Notes on Using the Sequence Transfer When sequence transfer is to be used, make sure that the DTCADMOD.SHORT bit is 0 (full-address mode) and the DTCCR.RRS bit is also 0 (transfer information read is not skipped). In addition, set the MRB.CHNE bit to 0 (chain transfer is disabled) when setting the MRB.INDX bit to 1 (start sequence transfer and refer the index table) or the MRB.SQEND bit to 1 (end the sequence transfer).
Page 293: I/O Ports
RX13T Group 17. I/O Ports I/O Ports 17.1 Overview The I/O ports function as a general I/O port, an I/O pin of a peripheral module, or an input pin for an interrupt. Some of the pins are also configurable as an I/O pin of a peripheral module or an input pin for an interrupt. All pins function as input pins immediately after a reset, and pin functions are switched by register settings.
Page 294 RX13T Group 17. I/O Ports Table 17.2 Port Functions Open Drain Drive Capacity High Current Port Input Pull-up Output Switching 5-V Tolerant PORT1 P10, P11 ○ ○ ○ ― ― PORT2 ○ ○ ○ ― ― P23, P24 ○ ○ ○...
Page 295: I/O Port Configuration
RX13T Group 17. I/O Ports 17.2 I/O Port Configuration Port 1: P10 , P11 Port 2: P22 to P24 Port 4: P40 to P44, P45 to P47 Port 7: P70 , P71 to P76 Port 9: P93, P94 Port A: PA2 , PA3 Port B: PB0 to PB3, PB4 , PB5...
Page 296 RX13T Group 17. I/O Ports Port3:P36/EXTAL 1 : ON 0 : OFF ODR0, ODR1 PODR Reading the port Main clock MOSCCR.MOSTP MOFCR.MOSEL 0 : ON 1 : OFF Port3:P37/XTAL 1 : ON 0 : OFF ODR0, ODR1 PODR Reading the port Note 1.
Page 297: Register Descriptions
RX13T Group 17. I/O Ports 17.3 Register Descriptions 17.3.1 Port Direction Register (PDR) Address(es): PORT1.PDR 0008 C001h, PORT2.PDR 0008 C002h, PORT3.PDR 0008 C003h, PORT4.PDR 0008 C004h, PORT7.PDR 0008 C007h, PORT9.PDR 0008 C009h, PORTA.PDR 0008 C00Ah, PORTB.PDR 0008 C00Bh, PORTD.PDR 0008 C00Dh Value after reset: Symbol Bit Name...
Page 298: Port Output Data Register (Podr)
RX13T Group 17. I/O Ports 17.3.2 Port Output Data Register (PODR) Address(es): PORT1.PODR 0008 C021h, PORT2.PODR 0008 C022h, PORT3.PODR 0008 C023h, PORT4.PODR 0008 C024h, PORT7.PODR 0008 C027h, PORT9.PODR 0008 C029h, PORTA.PODR 0008 C02Ah, PORTB.PODR 0008 C02Bh, PORTD.PODR 0008 C02Dh Value after reset: Symbol Bit Name Description...
Page 299: Port Input Data Register (Pidr)
RX13T Group 17. I/O Ports 17.3.3 Port Input Data Register (PIDR) Address(es): PORT1.PIDR 0008 C041h, PORT2.PIDR 0008 C042h, PORT3.PIDR 0008 C043h, PORT4.PIDR 0008 C044h, PORT7.PIDR 0008 C047h, PORT9.PIDR 0008 C049h, PORTA.PIDR 0008 C04Ah, PORTB.PIDR 0008 C04Bh, PORTD.PIDR 0008 C04Dh, PORTE.PIDR 0008 C04Eh Value after reset: x: Undefined Symbol...
Page 300: Port Mode Register (Pmr)
RX13T Group 17. I/O Ports 17.3.4 Port Mode Register (PMR) Address(es): PORT1.PMR 0008 C061h, PORT2.PMR 0008 C062h, PORT3.PMR 0008 C063h, PORT7.PMR 0008 C067h, PORT9.PMR 0008 C069h, PORTA.PMR 0008 C06Ah, PORTB.PMR 0008 C06Bh, PORTD.PMR 0008 C06Dh, PORTE.PMR 0008 C06Eh Value after reset: Symbol Bit Name Description...
Page 301: Open Drain Control Register 0 (Odr0)
RX13T Group 17. I/O Ports 17.3.5 Open Drain Control Register 0 (ODR0) Address(es): PORT1.ODR0 0008 C082h, PORT2.ODR0 0008 C084h, PORT7.ODR0 0008 C08Eh, PORT9.ODR0 0008 C092h, PORTA.ODR0 0008 C094h, PORTB.ODR0 0008 C096h, PORTD.ODR0 0008 C09Ah — — — Value after reset: Symbol Bit Name Description...
Page 302: Open Drain Control Register 1 (Odr1)
RX13T Group 17. I/O Ports 17.3.6 Open Drain Control Register 1 (ODR1) Address(es): PORT2.ODR1 0008 C085h, PORT3.ODR1 0008 C087h, PORT7.ODR1 0008 C08Fh, PORT9.ODR1 0008 C093h, PORTB.ODR1 0008 C097h, PORTD.ODR1 0008 C09Bh — — — — Value after reset: Symbol Bit Name Description Pm4 Output Type Select 0: CMOS output...
Page 303: Pull-Up Control Register (Pcr)
RX13T Group 17. I/O Ports 17.3.7 Pull-Up Control Register (PCR) Address(es): PORT1.PCR 0008 C0C1h, PORT2.PCR 0008 C0C2h, PORT3.PCR 0008 C0C3h, PORT4.PCR 0008 C0C4h, PORT7.PCR 0008 C0C7h, PORT9.PCR 0008 C0C9h, PORTA.PCR 0008 C0CAh, PORTB.PCR 0008 C0CBh, PORTD.PCR 0008 C0CDh Value after reset: Symbol Bit Name Description...
Page 304: Drive Capacity Control Register (Dscr)
RX13T Group 17. I/O Ports 17.3.8 Drive Capacity Control Register (DSCR) Address(es): PORT1.DSCR 0008 C0E1h, PORT2.DSCR 0008 C0E2h, PORT7.DSCR 0008 C0E7h, PORT9.DSCR 0008 C0E9h, PORTA.DSCR 0008 C0EAh, PORTB.DSCR 0008 C0EBh, PORTD.DSCR 0008 C0EDh Value after reset: Symbol Bit Name Description Pm0 Drive Capacity Control 0: Normal drive output 1: High-drive output...
Page 305: Initialization Of The Port Direction Register (Pdr)
RX13T Group 17. I/O Ports 17.4 Initialization of the Port Direction Register (PDR) Initialize reserved bits in the PDR register according to Table 17.3 and Table 17.4 .  The blank columns in Table 17.3 and Table 17.4 indicate the bits corresponding to the pins listed in Table 17.1, Specifications of I/O Ports .
Page 306: Handling Of Unused Pins
RX13T Group 17. I/O Ports 17.5 Handling of Unused Pins The configuration of unused pins is listed in Table 17.5 . Table 17.5 Unused Pin Configuration Pin Name Description (Always used as mode pins) RES# Connect this pin to VCC via a pull-up resistor. PE2/NMI Connect this pin to VCC via a pull-up resistor.
Page 307: Multi-Function Pin Controller (Mpc)
RX13T Group 18. Multi-Function Pin Controller (MPC) Multi-Function Pin Controller (MPC) 18.1 Overview The multi-function pin controller (MPC) is used to allocate input and output signals for peripheral modules and input interrupt signals to pins from among multiple ports. Table 18.1 shows the allocation of pin functions to multiple pins. The symbols ○ and × in the table indicate whether the pins are or are not present on the given package.
Page 308 RX13T Group 18. Multi-Function Pin Controller (MPC) Table 18.1 Allocation of Pin Functions to Multiple Pins (2/3) Package Allocation Module/Function Channel Pin Functions Port 48-pin 32-pin Multi-function timer unit 3 MTU3 MTIOC3A (input/output) ○ ○ ○ ○ MTIOC3B (input/output) ○ ○...
Page 309 RX13T Group 18. Multi-Function Pin Controller (MPC) Table 18.1 Allocation of Pin Functions to Multiple Pins (3/3) Package Allocation Module/Function Channel Pin Functions Port 48-pin 32-pin Serial communications SCI12 RXD12 (input) / SMISO12 (input/ ○ ○ interface output) / SSCL12 (input/output) / RXDX12 (input) TXD12 (output) / SMOSI12 (input/ ○...
Page 310: Register Descriptions
RX13T Group 18. Multi-Function Pin Controller (MPC) 18.2 Register Descriptions Registers and bits for pins that are not present due to differences according to the package are reserved. Write the value after a reset when writing to such bits. 18.2.1 Write-Protect Register (PWPR) Address(es): 0008 C11Fh B0WI PFSWE...
Page 311: P1N Pin Function Control Register (P1Npfs) (N = 0, 1)
RX13T Group 18. Multi-Function Pin Controller (MPC) 18.2.2 P1n Pin Function Control Register (P1nPFS) (n = 0, 1) Address(es): P10PFS 0008 C148h, P11PFS 0008 C149h ASEL ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function.
Page 312: P2N Pin Function Control Register (P2Npfs) (N = 2 To 4)
RX13T Group 18. Multi-Function Pin Controller (MPC) 18.2.3 P2n Pin Function Control Register (P2nPFS) (n = 2 to 4) Address(es): P22PFS 0008 C152h, P23PFS 0008 C153h, P24PFS 0008 C154h — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select...
Page 313: P4N Pin Function Control Register (P4Npfs) (N = 0 To 7)
RX13T Group 18. Multi-Function Pin Controller (MPC) 18.2.4 P4n Pin Function Control Register (P4nPFS) (n = 0 to 7) Address(es): P40PFS 0008 C160h, P41PFS 0008 C161h, P42PFS 0008 C162h, P43PFS 0008 C163h, P44PFS 0008 C164h, P45PFS 0008 C165h, P46PFS 0008 C166h, P47PFS 0008 C167h ASEL —...
Page 314: P7N Pin Function Control Register (P7Npfs) (N = 0 To 6)
RX13T Group 18. Multi-Function Pin Controller (MPC) 18.2.5 P7n Pin Function Control Register (P7nPFS) (n = 0 to 6) Address(es): P70PFS 0008 C178h, P71PFS 0008 C179h, P72PFS 0008 C17Ah, P73PFS 0008 C17Bh, P74PFS 0008 C17Ch, P75PFS 0008 C17Dh, P76PFS 0008 C17Eh —...
Page 315: P9N Pin Function Control Register (P9Npfs) (N = 3, 4)
RX13T Group 18. Multi-Function Pin Controller (MPC) 18.2.6 P9n Pin Function Control Register (P9nPFS) (n = 3, 4) Address(es): P93PFS 0008 C18Bh, P94PFS 0008 C18Ch — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function.
Page 316: Pan Pin Function Control Register (Panpfs) (N = 2, 3)
RX13T Group 18. Multi-Function Pin Controller (MPC) 18.2.7 PAn Pin Function Control Register (PAnPFS) (n = 2, 3) Address(es): PA2PFS 0008 C192h, PA3PFS 0008 C193h — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function.
Page 317: Pbn Pin Function Control Register (Pbnpfs) (N = 0 To 7)
RX13T Group 18. Multi-Function Pin Controller (MPC) 18.2.8 PBn Pin Function Control Register (PBnPFS) (n = 0 to 7) Address(es): PB0PFS 0008 C198h, PB1PFS 0008 C199h, PB2PFS 0008 C19Ah, PB3PFS 0008 C19Bh, PB4PFS 0008 C19Ch, PB5PFS 0008 C19Dh, PB6PFS 0008 C19Eh, PB7PFS 0008 C19Fh —...
Page 318: Pdn Pin Function Control Register (Pdnpfs) (N = 3 To 6)
RX13T Group 18. Multi-Function Pin Controller (MPC) 18.2.9 PDn Pin Function Control Register (PDnPFS) (n = 3 to 6) Address(es): PD3PFS 0008 C1ABh, PD4PFS 0008 C1ACh, PD5PFS 0008 C1ADh, PD6PFS 0008 C1AEh — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0...
Page 319: Pe2 Pin Function Control Register (Pe2Pfs)
RX13T Group 18. Multi-Function Pin Controller (MPC) 18.2.10 PE2 Pin Function Control Register (PE2PFS) Address(es): PE2PFS 0008 C1B2h — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see Table 18.9.
Page 320: Usage Notes
RX13T Group 18. Multi-Function Pin Controller (MPC) 18.3 Usage Notes 18.3.1 Procedure for Specifying Input/Output Pin Function Use the following procedure to specify the input/output pin functions. (1) Clear the port mode register (PMR) to 0 to select the general I/O port function. (2) Specify the assignments of input/output signals for peripheral functions to the desired pins.
Page 321: Note On Using Analog Functions
RX13T Group 18. Multi-Function Pin Controller (MPC) Table 18.10 Register Settings PmnPFS Item PMR.Bn PDR.Bn ASEL ISEL PSEL[4:0] Point to Note After a reset 00000b Pins function as general input port pins after release from the reset state. General input Set the ISEL bit to 1 if these are multiplexed with interrupt inputs.
Page 322: Multi-Function Timer Pulse Unit 3 (Mtu3C)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Multi-Function Timer Pulse Unit 3 (MTU3c) 19.1 Overview This MCU has an on-chip multi-function timer pulse unit 3 (MTU3c), consisting of six 16-bit timer channels. Table 19.1 shows the specifications of the MTU and Table 19.2 lists the functions of the MTU. Figure 19.1 shows a block diagram of the MTU.
Page 323 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.2 MTU Functions (1/2) MTU1 & MTU2 Item MTU0 MTU1 MTU2 (LWA = 1) MTU3 MTU4 MTU5 PCLKB/1 MTCLKA PCLKB/1 PCLKB/1 PCLKB/1 Count clock PCLKB/1 PCLKB/1 PCLKB/2 PCLKB/2 PCLKB/2 PCLKB/2 PCLKB/2 PCLKB/2 MTCLKB...
Page 324 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.2 MTU Functions (2/2) MTU1 & MTU2 Item MTU0 MTU1 MTU2 (LWA = 1) MTU3 MTU4 MTU5  A/D converter start A/D converter start request — — — — — —...
Page 325 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Interrupt request signals MTU3: TGIA3 TGIB3 TGIC3 I/O pins TGID3 MTU3 : MTIOC3A TCIV3 MTIOC3B MTU4: TGIA4 MTIOC3C MTIOC3D TGIB4 TGIC4 MTU4 : MTIOC4A TGID4 MTIOC4B TCIV4 MTIOC4C MTIOC4D Clock input Internal clock: PCLKB PCLKB/2...
Page 326 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.3 shows the configuration of pins for the MTU . Table 19.3 Pin Configuration of the MTU Channel Pin Name Function MTCLKA Input External clock A input pin (MTU1 and MTU2 phase counting mode A phase input) MTCLKB Input External clock B input pin (MTU1 and MTU2 phase counting mode B phase input)
Page 327: Register Descriptions
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2 Register Descriptions 19.2.1 Timer Control Register (TCR)  MTU0.TCR, MTU1.TCR, MTU2.TCR, MTU3.TCR, MTU4.TCR Address(es): MTU0.TCR 0009 5300h, MTU1.TCR 0009 5380h, MTU2.TCR 0009 5400h, MTU3.TCR 0009 5200h, MTU4.TCR 0009 5201h CCLR[2:0] CKEG[1:0] TPSC[2:0] Value after reset:...
Page 328 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.4 CCLR[2:0] (MTU0, MTU3, MTU4) Bit 7 Bit 6 Bit 5 Channel CCLR[2] CCLR[1] CCLR[0] Description MTU0 TCNT clearing disabled MTU3 TCNT cleared by TGRA compare match/input capture MTU4 TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing in another channel performing synchronous clearing/ synchronous operation* TCNT clearing disabled...
Page 329: Timer Control Register 2 (Tcr2)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.2 Timer Control Register 2 (TCR2)  MTU0.TCR2, MTU3.TCR2, MTU4.TCR2 Address(es): MTU0.TCR2 0009 5328h, MTU3.TCR2 0009 524Ch, MTU4.TCR2 0009 524Dh — — — — — TPSC2[2:0] Value after reset:  MTU1.TCR2, MTU2.TCR2 Address(es): MTU1.TCR2 0009 5394h, MTU2.TCR2 0009 540Ch —...
Page 330 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c)  MTU5.TCR2U, MTU5.TCR2V, MTU5.TCR2W Address(es): MTU5.TCR2U 0009 5485h, MTU5.TCR2V 0009 5495h, MTU5.TCR2W 0009 54A5h — — — CKEG[1:0] TPSC2[2:0] Value after reset: Symbol Bit Name Description b2 to b0 TPSC2[2:0] Time Prescaler Select Refer to Table 19.10.
Page 331 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.7 TPSC[2:0], TPSC2[2:0] (MTU1) TCR2 register TCR register Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 Channel TPSC2[2] TPSC2[1] TPSC2[0] TPSC[2] TPSC[1] TPSC[0] Description MTU1 Internal clock: counts on PCLKB/1 Internal clock: counts on PCLKB/4 Internal clock: counts on PCLKB/16 Internal clock: counts on PCLKB/64...
Page 332 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.9 TPSC[2:0], TPSC2[2:0] (MTU3, MTU4) TCR2 register TCR register Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 Channel TPSC2[2] TPSC2[1] TPSC2[0] TPSC[2] TPSC[1] TPSC[0] Description MTU3 Internal clock: counts on PCLKB/1 MTU4 Internal clock: counts on PCLKB/4...
Page 333: Timer Mode Register 1 (Tmdr1)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.3 Timer Mode Register 1 (TMDR1)  MTU0.TMDR1 Address(es): MTU0.TMDR1 0009 5301h — MD[3:0] Value after reset:  MTU1.TMDR1, MTU2.TMDR1 Address(es): MTU1.TMDR1 0009 5381h, MTU2.TMDR1 0009 5401h — — — — MD[3:0] Value after reset: ...
Page 334 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.11 Operating Mode Setting by MD[3:0] Bits (MTU0 to MTU4) Bit 3 Bit 2 Bit 1 Bit 0 MD[3] MD[2] MD[1] MD[0] Description Normal mode      Setting prohibited PWM mode 1 ...
Page 335: Timer Mode Register 2 (Tmdr2A)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) BFE Bit (Buffer Operation E) This bit specifies whether to operate MTU0.TGRE and MTU0.TGRF in the normal way or to use them together for buffer operation. Compare match with TGRF occurs even when TGRF is used as a buffer register. In MTU0 to MTU4, this bit is reserved.
Page 336: Timer Mode Register 3 (Tmdr3)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.5 Timer Mode Register 3 (TMDR3) Address(es): MTU1.TMDR3 0009 5391h PHCKS — — — — — — Value after reset: Symbol Bit Name Description MTU1/MTU2 Combination 0: 16-bit access is enabled. Longword Access Control 1: 32-bit access is enabled.
Page 337: Timer I/O Control Register (Tior)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.6 Timer I/O Control Register (TIOR)  MTU0.TIORH, MTU1.TIOR, MTU2.TIOR, MTU3.TIORH, MTU4.TIORH Address(es): MTU0.TIORH 0009 5302h, MTU1.TIOR 0009 5382h, MTU2.TIOR 0009 5402h, MTU3.TIORH 0009 5204h, MTU4.TIORH 0009 5206h IOB[3:0] IOA[3:0] Value after reset: Symbol Bit Name Description...
Page 338 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c)  MTU5.TIORU, MTU5.TIORV, MTU5.TIORW Address(es): MTU5.TIORU 0009 5486h, MTU5.TIORV 0009 5496h, MTU5.TIORW 0009 54A6h — — — IOC[4:0] Value after reset: Symbol Bit Name Description b4 to b0 IOC[4:0] I/O Control C Refer to the following table.
Page 339 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.14 TIORL (MTU0) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD[3] IOD[2] IOD[1] IOD[0] TGRD Register Function MTIOC0D Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 340 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.16 TIOR (MTU2) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] TGRB Register Function MTIOC2B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 341 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.18 TIORL (MTU3) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD[3] IOD[2] IOD[1] IOD[0] TGRD Register Function MTIOC3D Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 342 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.20 TIORL (MTU4) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD[3] IOD[2] IOD[1] IOD[0] TGRD Register Function MTIOC4D Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 343 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.22 TIORL (MTU0) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC[3] IOC[2] IOC[1] IOC[0] TGRC Register Function MTIOC0C Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 344 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.24 TIOR (MTU2) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA[3] IOA[2] IOA[1] IOA[0] TGRA Register Function MTIOC2A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 345 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.26 TIORL (MTU3) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC[3] IOC[2] IOC[1] IOC[0] TGRC Register Function MTIOC3C Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 346 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.28 TIORL (MTU4) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC[3] IOC[2] IOC[1] IOC[0] TGRC Register Function MTIOC4C Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 347 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.29 TIORU, TIORV, and TIORW (MTU5) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description TGRU, TGRV, TGRW IOC[4] IOC[3] IOC[2] IOC[1] IOC[0] Registers Function MTIC5U, MTIC5V, MTIC5W Pin Function Output compare register No function Setting prohibited...
Page 348: Timer Compare Match Clear Register (Tcntcmpclr)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.7 Timer Compare Match Clear Register (TCNTCMPCLR) Address(es): MTU5.TCNTCMPCLR 0009 54B6h CMPCL CMPCL CMPCL — — — — — Value after reset: Symbol Bit Name Description CMPCLR5W TCNT Compare Clear 5W 0: Disables MTU5.TCNTW to be cleared to 0000h at MTU5.TCNTW and MTU5.TGRW compare match or input capture...
Page 349: Timer Interrupt Enable Register (Tier)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.8 Timer Interrupt Enable Register (TIER)  MTU1.TIER, MTU2.TIER Address(es): MTU1.TIER 0009 5384h, MTU2.TIER 0009 5404h TTGE — TCIEU TCIEV — — TGIEB TGIEA Value after reset:  MTU0.TIER, MTU3.TIER Address(es): MTU0.TIER 0009 5304h, MTU3.TIER 0009 5208h TTGE —...
Page 350 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) TGIEA and TGIEB Bits (TGR Interrupt Enable A and B) Each bit enables or disables interrupt requests (TGIn) (n = A, B). TGIEC and TGIED Bits (TGR Interrupt Enable C and D) Each bit enables or disables an interrupt request (TGIn) (n = C, D).
Page 351 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c)  MTU5.TIER Address(es): MTU5.TIER 0009 54B2h TGIE5 TGIE5V TGIE5 — — — — — Value after reset: Symbol Bit Name Description TGIE5W TGR Interrupt Enable 5W 0: Interrupt requests TGIW5 disabled 1: Interrupt requests TGIW5 enabled TGIE5V TGR Interrupt Enable 5V...
Page 352: Timer Status Register (Tsr)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.9 Timer Status Register (TSR)  MTU1.TSR, MTU2.TSR Address(es): MTU1.TSR 0009 5385h, MTU2.TSR 0009 5405h TCFD — — — — — — — Value after reset:  MTU3.TSR, MTU4.TSR Address(es): MTU3.TSR 0009 522Ch, MTU4.TSR 0009 522Dh TCFD —...
Page 353: Timer Buffer Operation Transfer Mode Register (Tbtm)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.10 Timer Buffer Operation Transfer Mode Register (TBTM)  MTU0.TBTM Address(es): MTU0.TBTM 0009 5326h — — — — — TTSE TTSB TTSA Value after reset:  MTU3.TBTM, MTU4.TBTM Address(es): MTU3.TBTM 0009 5238h, MTU4.TBTM 0009 5239h —...
Page 354: Timer Input Capture Control Register (Ticcr)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.11 Timer Input Capture Control Register (TICCR) Address(es): MTU1.TICCR 0009 5390h — — — — I2BE I2AE I1BE I1AE Value after reset: Symbol Bit Name Description I1AE Input Capture Enable 0: Does not include the MTIOC1A pin in the MTU2.TGRA input capture conditions 1: Includes the MTIOC1A pin in the MTU2.TGRA input capture conditions...
Page 355: Timer Counter (Tcnt)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.12 Timer Counter (TCNT) Address(es): MTU0.TCNT 0009 5306h, MTU1.TCNT 0009 5386h, MTU2.TCNT 0009 5406h, MTU3.TCNT 0009 5210h, MTU4.TCNT 0009 5212h, MTU5.TCNTU 0009 5480h, MTU5.TCNTV 0009 5490h, MTU5.TCNTW 0009 54A0h Value after reset: Note: TCNT must not be accessed in 8 bits;...
Page 356: Timer General Register (Tgr)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.14 Timer General Register (TGR) Address(es): MTU0.TGRA 0009 5308h, MTU0.TGRB 0009 530Ah, MTU0.TGRC 0009 530Ch, MTU0.TGRD 0009 530Eh, MTU0.TGRE 0009 5320h, MTU0.TGRF 0009 5322h, MTU1.TGRA 0009 5388h, MTU1.TGRB 0009 538Ah, MTU2.TGRA 0009 5408h, MTU2.TGRB 0009 540Ah, MTU3.TGRA 0009 5218h, MTU3.TGRB 0009 521Ah, MTU3.TGRC 0009 5224h, MTU3.TGRD 0009 5226h, MTU3.TGRE 0009 5272h, MTU4.TGRA 0009 521Ch, MTU4.TGRB 0009 521Eh, MTU4.TGRC 0009 5228h, MTU4.TGRD 0009 522Ah, MTU4.TGRE 0009 5274h, MTU4.TGRF 0009 5276h,...
Page 357: Timer Start Registers (Tstra, Tstr)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.16 Timer Start Registers (TSTRA, TSTR)  MTU.TSTRA (for MTU0, MTU1, MTU2, MTU3, and MTU4) Address(es): MTU.TSTRA 0009 5280h CST4 CST3 — — — CST2 CST1 CST0 Value after reset: Symbol Bit Name Description CST0...
Page 358 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c)  MTU5.TSTR Address(es): MTU5.TSTR 0009 54B4h — — — — — CSTU5 CSTV5 CSTW5 Value after reset: Symbol Bit Name Description CSTW5 Counter Start W5 0: MTU5.TCNTW counting is stopped 1: MTU5.TCNTW performs count operation CSTV5 Counter Start V5 0: MTU5.TCNTV counting is stopped...
Page 359: Timer Synchronous Register (Tsyra)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.17 Timer Synchronous Register (TSYRA) Address(es): MTU.TSYRA 0009 5281h SYNC4 SYNC3 — — — SYNC2 SYNC1 SYNC0 Value after reset: Symbol Bit Name Description SYNC0 Timer Synchronous 0: MTU0.TCNT operates independently (TCNT setting/clearing is not Operation 0 related to other channels).
Page 360: Timer Counter Synchronous Start Register (Tcsystr)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.18 Timer Counter Synchronous Start Register (TCSYSTR) Address(es): MTU.TCSYSTR 0009 5282h SCH0 SCH1 SCH2 SCH3 SCH4 — — — Value after reset: Symbol Bit Name Description b2 to b0 — Reserved These bits are read as 0.
Page 361: Timer Read/Write Enable Register (Trwera)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.19 Timer Read/Write Enable Register (TRWERA) Address(es): MTU.TRWERA 0009 5284h — — — — — — — Value after reset: Symbol Bit Name Description Read/Write Enable 0: Read/write access to the registers is disabled 1: Read/write access to the registers is enabled b7 to b1 —...
Page 362: Timer Output Master Enable Register (Toera)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.20 Timer Output Master Enable Register (TOERA) Address(es): MTU.TOERA 0009 520Ah — — OE4D OE4C OE3D OE4B OE4A OE3B Value after reset: Symbol Bit Name Description OE3B Master Enable MTIOC3B 0: MTU output is disabled* 1: MTU output is enabled OE4A Master Enable MTIOC4A...
Page 363: Timer Output Control Register 1 (Tocr1A)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.21 Timer Output Control Register 1 (TOCR1A) Address(es): MTU.TOCR1A 0009 520Eh — PSYE — — TOCL TOCS OLSN OLSP Value after reset: Symbol Bit Name Description OLSP Output Level Select P* Refer to Table 19.30.
Page 364 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.30 Output Level Select Function Bit 0 Function Compare Match Output OLSP Initial Output Active Level Up-Counting Down-Counting High level Low level Low level High level Low level High level High level Low level Table 19.31...
Page 365: Timer Output Control Register 2 (Tocr2A)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.22 Timer Output Control Register 2 (TOCR2A) Address(es): MTU.TOCR2A 0009 520Fh BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Value after reset: Symbol Bit Name Description OLS1P Output Level Select 1P* This bit selects the output level on MTIOC3B in reset- synchronized PWM mode and complementary PWM mode.
Page 366 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.33 MTIOCmD Output Level Select Function Bit 1 Function Compare Match Output OLS1N Initial Output Active Level Up-Counting Down-Counting High level Low level High level Low level Low level High level Low level High level m = 3...
Page 367 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.38 Setting of TOCR2j.BF[1:0] Bits Bit 7 Bit 6 Description BF[1] BF[0] Complementary PWM Mode Reset-Synchronized PWM Mode Does not transfer data from the buffer register (TOLBRj) Does not transfer data from the buffer register to TOCR2j.
Page 368: Timer Output Level Buffer Register (Tolbra)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.23 Timer Output Level Buffer Register (TOLBRA) Address(es): MTU.TOLBRA 0009 5236h — — OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Value after reset: Symbol Bit Name Description OLS1P Output Level Select 1P Specify the buffer value to be transferred to the OLS1P bit in TOCR2j.
Page 369: Timer Gate Control Register A (Tgcra)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.24 Timer Gate Control Register A (TGCRA) Address(es): MTU.TGCRA 0009 520Dh — Value after reset: Symbol Bit Name Description Output Phase Switch These bits turn on or off the positive-phase/negative-phase output. The setting of these bits is valid only when the FB bit is set to 1.
Page 370: Timer Subcounter (Tcntsa)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.39 Output Level Select Function Bit 2 Bit 1 Bit 0 Function MTIOC3B MTIOC4A MTIOC4B MTIOC3D MTIOC4C MTIOC4D U Phase V Phase W Phase U Phase V Phase W Phase 19.2.25 Timer Subcounter (TCNTSA) Address(es): MTU.TCNTSA 0009 5220h...
Page 371: Timer Period Buffer Register (Tcbra)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.27 Timer Period Buffer Register (TCBRA) Address(es): MTU.TCBRA 0009 5222h Value after reset: Note: TCBRA must not be accessed in 8 bits; it should be accessed in 16 bits. TCBRA is a 16-bit readable/writable register, used only in complementary PWM mode, that function as buffer register for TCDRA.
Page 372: Timer Dead Time Enable Register (Tdera)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.29 Timer Dead Time Enable Register (TDERA) Address(es): MTU.TDERA 0009 5234h — — — — — — — TDER Value after reset: Symbol Bit Name Description TDER Dead Time Enable 0: No dead time is generated R/(W) 1: Dead time is generated* b7 to b1...
Page 373: Timer Buffer Transfer Set Register (Tbtera)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.30 Timer Buffer Transfer Set Register (TBTERA) Address(es): MTU.TBTERA 0009 5232h — — — — — — BTE[1:0] Value after reset: Symbol Bit Name Description b1, b0 BTE[1:0] Buffer Transfer Disable and These bits enable or disable transfer from the buffer registers* Interrupt Skipping Link Setting used in complementary PWM mode to the temporary registers,...
Page 374: Timer Waveform Control Register (Twcra)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.31 Timer Waveform Control Register (TWCRA) Address(es): MTU.TWCRA 0009 5260h — — — — — — Value after reset: Symbol Bit Name Description Waveform Retain Enable 0: Initial values specified in TOCR1A and TOCR2A are output R/(W) 1: Initial output is inhibited b6 to b1...
Page 375: Noise Filter Control Register N (Nfcrn) (N = 0 To 4, C)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.32 Noise Filter Control Register n (NFCRn) (n = 0 to 4, C)  MTU0.NFCR0, MTU1.NFCR1, MTU2.NFCR2, MTU3.NFCR3, MTU4.NFCR4 Address(es): MTU0.NFCR0 0009 5290h, MTU1.NFCR1 0009 5291h, MTU2.NFCR2 0009 5292h, MTU3.NFCR3 0009 5293h, MTU4.NFCR4 0009 5294h —...
Page 376 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) NFCS[1:0] Bits (Noise Filter Clock Select) These bits set the sampling interval for the noise filters. When setting the NFCS[1:0] bits, wait for two cycles of the selected sampling interval before setting the input-capture function. When the NFCS[1:0] bits are set to 11b, i.e. selecting the external clock as the source to drive counting, wait for two cycles of the external clock before setting the input capture function.
Page 377: Noise Filter Control Register 5 (Nfcr5)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) NFCS[1:0] Bits (Noise Filter Clock Select) These bits set the sampling interval for the noise filters. After setting the NFCS[1:0] bits, wait for two cycles of the selected sampling interval to set the input capture function. 19.2.33 Noise Filter Control Register 5 (NFCR5) Address(es): MTU5.NFCR5 0009 5295h...
Page 378: Timer A/D Converter Start Request Control Register (Tadcr)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.34 Timer A/D Converter Start Request Control Register (TADCR) Address(es): MTU4.TADCR 0009 5240h BF[1:0] — — — — — — UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Value after reset: Symbol Bit Name Description...
Page 379 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.41 Setting of Transfer Timing by TADCR.BF[1:0] Bits (MTU4) Bit 15 Bit 14 Description In Complementary PWM In Reset-Synchronized BF[1] BF[0] Mode PWM Mode In PWM Mode 1 In Normal Mode Data is not transferred from Data is not transferred from Data is not transferred from...
Page 380: Timer A/D Converter Start Request Cycle Set Registers (Tadcora, Tadcorb)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.35 Timer A/D Converter Start Request Cycle Set Registers (TADCORA, TADCORB) Address(es): MTU4.TADCORA 0009 5244h, MTU4.TADCORB 0009 5246h Value after reset: Note: TADCORA and TADCORB must not be accessed in 8 bits; it should be accessed in 16 bits. Note 1.
Page 381: Timer Interrupt Skipping Mode Register (Titmra)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.37 Timer Interrupt Skipping Mode Register (TITMRA) Address(es): MTU.TITMRA 0009 523Ah — — — — — — — TITM Value after reset: Symbol Bit Name Description TITM Interrupt Skipping Function Select Selects one of the two types of interrupt skipping functions.
Page 382: Timer Interrupt Skipping Set Register 1 (Titcr1A)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.38 Timer Interrupt Skipping Set Register 1 (TITCR1A) Address(es): MTU.TITCR1A 0009 5230h T3AEN T3ACOR[2:0] T4VEN T4VCOR[2:0] Value after reset: Symbol Bit Name Description b2 to b0 T4VCOR[2:0] TCIV4 Interrupt Skipping Count These bits specify the TCIV4 interrupt skipping count within Setting the range from 0 to 7.*...
Page 383: Timer Interrupt Skipping Counter 1 (Titcnt1A)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.39 Timer Interrupt Skipping Counter 1 (TITCNT1A) Address(es): MTU.TITCNT1A 0009 5231h — T3ACNT[2:0] — T4VCNT[2:0] Value after reset: Symbol Bit Name Description b2 to b0 T4VCNT[2:0] TCIV4 Interrupt Counter While the T4VEN bit in TITCR1A is set to 1, the count in these bits is incremented every time a TCIV4 interrupt occurs.
Page 384: Timer Interrupt Skipping Set Register 2 (Titcr2A)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.40 Timer Interrupt Skipping Set Register 2 (TITCR2A) Address(es): MTU.TITCR2A 0009 523Bh — — — — — TRG4COR[2:0] Value after reset: Symbol Bit Name Description b2 to b0 TRG4COR[2:0] TRG4AN/TRG4BN Interrupt These bits specify the TRG4AN/TRG4BN interrupt skipping Skipping Count Setting count within the range from 0 to 7.
Page 385: Timer Interrupt Skipping Counter 2 (Titcnt2A)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.41 Timer Interrupt Skipping Counter 2 (TITCNT2A) Address(es): MTU.TITCNT2A 0009 523Ch — — — — — TRG4CNT[2:0] Value after reset: Symbol Bit Name Description b2 to b0 TRG4CNT[2:0] TRG4AN/TRG4BN These bits start counting from the value set in TRG4COR[2:0] Interrupt Counter and the count decrements every time TRG4AN or TRG4BN is generated.
Page 386: A/D Conversion Start Request Select Register 0 (Tadstrgr0)
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.2.42 A/D Conversion Start Request Select Register 0 (TADSTRGR0) Address(es): MTU.TADSTRGR0 0009 5D30h — — — TADSTRS0[4:0] Value after reset: Symbol Bit Name Description b4 to b0 TADSTRS0[4:0] A/D Conversion Start Request These bits select the A/D conversion start request for Select for ADSM0 Pin Output generating the frame synchronization signal to be output from...
Page 387: Operation
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3 Operation 19.3.1 Basic Functions Each channel has TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR register can be used as an input capture register or an output compare register. (1) Counter Operation When one of bits CST0 to CST4 in the TSTRA register, and bits CSTU5, CSTV5, and CSTW5 in the MTU5.TSTR register is set to 1, TCNT for the corresponding channel begins counting.
Page 388 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (b) Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the TCNT counters are all designated as free-running counters. When the CSTn bit in TSTRA or MTU5.TSTR is set to 1, the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from FFFFh to 0000h), an interrupt request is issued to the CPU if the corresponding TIER.TCIEV bit is 1.
Page 389 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (2) Waveform Output by Compare Match Upon compare match, low, high, or toggle output from the corresponding pin can be performed. (a) Example of Procedure for Setting Waveform Output by Compare Match Figure 19.7 shows an example of the procedure for setting waveform output by compare match Output selection [1] Enable TOERA output when outputting a waveform...
Page 390 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (b) Examples of Waveform Output Operation Figure 19.8 shows an example of low output and high output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that high is output by compare match A and low is output by compare match B.
Page 391 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the MTIOCnm pin (n = 0 to 4; m = A to D) or MTIC5m pin (m = U, V, W) input edge.
Page 392 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (b) Example of Input Capture Operation Figure 19.11 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the MTIOCnA pin input capture input edge, the falling edge has been selected as the MTIOCnB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 393: Synchronous Operation
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be modified simultaneously (synchronous setting). In addition, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR.
Page 394 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (2) Example of Synchronous Operation Figure 19.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for MTU0 to MTU 2, MTU0.TGRB compare match has been set as the counter clearing source in MTU0, and synchronous clearing has been set for the counter clearing source in MTU1 and MTU2.
Page 395: Buffer Operation
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.3 Buffer Operation Buffer operation, provided for MTU0, MTU3, and MTU4, enables TGRC and TGRD to be used as buffer registers. In MTU0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 396 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (1) Example of Buffer Operation Setting Procedure Figure 19.16 shows an example of the buffer operation setting procedure. Buffer operation Select TGR function [1] Designate TGR as an input capture register or output compare register by means of TIOR.
Page 397 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (b) When TGR is an Input Capture Register Figure 19.18 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the MTIOCnA pin input capture input edge.
Page 398 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (3) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for MTU0 or in PWM mode 1 for MTU3 and MTU4 by setting the buffer operation transfer mode registers (MTUn.TBTM (n = 0, 3, 4)).
Page 399: Cascaded Operation
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.4 Cascaded Operation In cascaded operation, two 16-bit counters in different channels are used together as a 32-bit counter. There are two functions for connecting MTU1 and MTU2 to use as a 32-bit counter: cascade connection to be set when the MTU1.TMDR3.LWA bit is 0, and cascade connection 32-bit phase counting mode to be set when the MTU1.TMDR3.LWA bit is 1.
Page 400 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (1) Example of Cascaded Operation Setting Procedure Figure 19.20 shows an example of the cascaded operation setting procedure. Cascaded operation [1] Set bits TPSC[2:0] in TCR to 111b in MTU1 to Set cascading select MTU2.TCNT overflow/underflow counting.
Page 401 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (3) Cascaded Operation Example (b) Figure 19.22 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the I2AE bit in TICCR has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the MTU1.TIOR.IOA[3:0] bits have selected the MTIOC1A rising edge for the input capture timing while the MTU2.TIOR.IOA[3:0] bits have selected the MTIOC2A rising edge for the input capture timing.
Page 402 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (4) Cascaded Operation Example (c) Figure 19.23 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE and I1AE bits have been set to 1 to include the MTIOC2A and MTIOC1A pins in the MTU1.TGRA and MTU2.TGRA input capture conditions, respectively.
Page 403 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (5) Cascaded Operation Example (d) Figure 19.24 illustrates the operation when MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE bit has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the IOA[3:0] bits in MTU1.TIOR have selected occurrence of MTU0.TGRA compare match or input capture for the input capture timing while the IOA[3:0] bits in MTU2.TIOR have selected the MTIOC2A rising edge for the input capture timing.
Page 404: Pwm Modes
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.5 PWM Modes PWM modes are provided to output PWM waveforms from the external pins. The output level can be selected as low, high, or toggle output in response to a compare match of each TGR. PWM waveforms in the range of 0% to 100% duty cycle can be output according to the TGR settings.
Page 405 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (1) Example of PWM Mode Setting Procedure Figure 19.25 shows an example of the PWM mode setting procedure. PWM mode [1] Enable TOERA output when outputting a waveform from the MTIOC pin of MTU3 and MTU4. Enable waveform output [2] Select the count clock source with bits TPSC[2:0] in TCR.
Page 406 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Figure 19.27 shows an example of operation in PWM mode 2. In this example, synchronous operation is designated for MTU0 and MTU1, MTU1.TGRB compare match is set as the TCNT clearing source, and low is set as the initial output value and high as the output value for the other TGR registers (MTU0.TGRA to MTU0.TGRD and MTU1.TGRA), outputting 5-phase PWM waveforms.
Page 407 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Figure 19.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode 1. In this example, TGRA compare match is set as the TCNT clearing source, a low level is set as the initial output value and output value for TGRA, and a high level is set as the output value for TGRB.
Page 408: Phase Counting Mode
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.6 Phase Counting Mode There are two phase counting modes: 16-bit phase counting mode in which MTU1 and MTU2 operate independently, and cascade connection 32-bit phase counting mode in which MTU1 and MTU2 are cascaded. In phase counting mode, the phase difference between two external input clocks is detected and the corresponding TCNT is incremented or decremented.
Page 409 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (1) Example of 16-Bit Phase Counting Mode Setting Procedure Figure 19.29 shows an example of the phase counting mode setting procedure. 16-bit phase counting mode [1] Set the TMDR3.LWA bit of MTU1 to 0. Set the TMDR1.MD[3:0] bits to select the 16-bit select phase phase counting mode.
Page 410 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (2) Examples of 16-Bit Phase Counting Mode Operation In phase counting mode, TCNT is incremented or decremented according to the phase difference between two external clocks. There are five modes according to the count conditions. Each mode operates under the condition PHCKSEL = 1, which means the phase clock for MTU1 is input from MTCLKA or MTCLKB and that for MTU2 is input from MTCLKC or MTCLKD.
Page 411 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (b) Phase Counting Mode 2 Figure 19.31 to Figure 19.33 show the examples of operation in phase counting mode 2 and Table 19.52 summarizes the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2)
Page 412 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.52 Up-Counting and Down-Counting Conditions in Phase Counting Mode 2 MTCLKA (MTU1) MTCLKB (MTU1) PCB[1:0] MTCLKC (MTU2) MTCLKD (MTU2) Operation High Not counted (Don’t care) High Up-counting High Not counted (Don’t care) High Down-counting High...
Page 413 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Phase Counting Mode 3 Figure 19.34 to Figure 19.36 show the examples of operation in phase counting mode 3 and Table 19.53 summarizes the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2)
Page 414 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value Down-counting Up-counting Time Figure 19.36 Example of Operation in Phase Counting Mode 3 (When MTUn.TCR2.PCB[1:0] = 1xb (n = 1, 2)) Table 19.53 Up-Counting and Down-Counting Conditions in Phase Counting Mode 3 MTCLKA (MTU1)
Page 415 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (d) Phase Counting Mode 4 Figure 19.37 shows an example of operation in phase counting mode 4, and Table 19.54 summarizes the TCNT up- counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value...
Page 416 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (e) Phase Counting Mode 5 Figure 19.38 and Figure 19.39 show the examples of operation in phase counting mode 5 and Table 19.55 summarizes the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2)
Page 417 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.55 Up-Counting and Down-Counting Conditions in Phase Counting Mode 5 MTCLKA (MTU1) MTCLKB (MTU1) PCB[1:0] MTCLKC (MTU2) MTCLKD (MTU2) Operation High Not counted (Don’t care) High Up-counting High Not counted (Don’t care) High Up-counting High...
Page 418 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (3) 16-Bit Phase Counting Mode Application Example Figure 19.40 shows an example in which MTU1 is in phase counting mode, and MTU1 is coupled with MTU0 to input 2-phase encoder pulses of a servo motor in order to detect position or speed. MTU1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to MTCLKA and MTCLKB.
Page 419: Cascade Connection 32-Bit Phase Counting Mode
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.6.2 Cascade Connection 32-Bit Phase Counting Mode When MTU1 is set to phase counting mode by setting MTU1.TMDR3.LWA = 1, MTU1 and MTU2 are connected to operate in cascade connection 32-bit phase counting mode. When this mode is used, the TCR, TCR2, TIOR, TIER, TGR, and TSR registers are controlled by MTU1 and the settings of MTU2 are disabled.
Page 420: Reset-Synchronized Pwm Mode
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three phases of positive and negative PWM waveforms (six phases in total) that share a common wave transition point can be output by combining MTU3 and MTU4. When set for reset-synchronized PWM mode, the MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B, and MTIOC4D pins function as PWM output pins and timer counter 3 (MTU3.TCNT) functions as an up-counter.
Page 421 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (1) Example of Procedure for Setting Reset-Synchronized PWM Mode Figure 19.42 shows an example of procedure for setting the reset-synchronized PWM mode. [1] Set the TSTRA.CST3 and TSTRA.CST4 bits to 0 to stop the TCNT Reset-synchronized count operation.
Page 422 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (2) Example of Reset-Synchronized PWM Mode Operation Figure 19.43 shows an example of operation in the reset-synchronized PWM mode. MTU3.TCNT and MTU4.TCNT operate as up-counters. The counters are cleared when a compare match occurs between MTU3.TCNT and MTU3.TGRA, and then begin incrementing from 0000h.
Page 423: Complementary Pwm Mode
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.8 Complementary PWM Mode In complementary PWM mode, dead time can be set for PWM waveforms to be output. The dead time is the period during which the upper and lower arm transistors are set to the inactive level in order to prevent short-circuiting of the arms.
Page 424 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.60 Register Settings for Complementary PWM Mode (2/2) Channel Counter/ Register Description Read/Write from CPU Timer dead time data register A Set MTU4.TCNT and MTU3.TCNT offset value (dead Maskable by TRWERA setting* (TDDRA) time value) Timer period data register A...
Page 425 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) MTU3. TCBRA TGRC MTU3. TDDRA TCDRA TGRA MTIOC3A Match Comparator signal MTIOC3B MTIOC3D MTU3. MTU4. TCNTSA TCNT TCNT MTIOC4A MTIOC4B MTIOC4C Comparator MTIOC4D Match signal External cutoff input POE0# MTU4. MTU3. MTU4.
Page 426 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (1) Example of Complementary PWM Mode Setting Procedure Figure 19.45 shows an example of the complementary PWM mode setting procedure. [1] Set the TSTRA.CST3 and TSTRA.CST4 bits to 0 to stop the TCNT count operation. Specify complementary PWM mode while MTU3.TCNT and MTU4.TCNT are stopped.
Page 427 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (2) Outline of Complementary PWM Mode Operation In complementary PWM mode, six phases (three positive and three negative) PWM waveforms can be output. Figure 19.46 illustrates counter operation in complementary PWM mode (MTU3 and MTU4), and Figure 19.47 shows an example of operation in complementary PWM mode.
Page 428 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (b) Register Operation In complementary PWM mode, nine registers (compare registers, buffer registers, and temporary registers) are used to control the duty ratio for the PWM output. Figure 19.47 shows an example of operation in complementary PWM mode (MTU3 and MTU4).
Page 429 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Transfer from temporary Transfer from temporary MTU3.TCNT register register MTU4.TCNT to compare register to compare register TCNTSA MTU3.TGRA TCNTSA TCDRA MTU3.TCNT MTU4.TGRA MTU4.TCNT MTU4.TGRC TDDRA 0000h Buffer register 6400h 0080h MTU4.TGRC 0080h Temporary register 6400h...
Page 430 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Initial Setting In complementary PWM mode, there are nine registers that require initial setting. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with MTU3.TMDR1.MD[3:0] bits, initial values should be set in the following registers.
Page 431 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Dead Time Suppressing Dead time generation is suppressed by setting the TDER bit in the timer dead time enable register (TDERA) to 0. TDERA can be set to 0 only when 0 is written to it after reading TDER = 1. MTU3.TGRA and MTU3.TGRC should be set to 1/2 PWM period + 1 and the timer dead time data register (TDDRA) should be set to 1.
Page 432 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (g) PWM Period Setting In complementary PWM mode, the PWM period is set in two registers—MTU3.TGRA, in which the MTU3.TCNT upper limit value is set, and TCDRA, in which the MTU4.TCNT upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: With dead time: MTU3.TGRA setting = TCDRA setting + TDDRA setting Without dead time: MTU3.TGRA setting = TCDRA setting + 1...
Page 433 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (h) Register Data Updating The buffer registers are used to update the data in five compare registers for the PWM duty and PWM period in complementary PWM mode. The update data can be written to the buffer register at any time. There is a temporary register between each of these registers and its buffer register.
Page 434 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Figure 19.50 Example of Data Updating in Complementary PWM Mode (MTU3 and MTU4) R01UH0822EJ0100 Rev.1.00 Page 434 of 1041 Jul 31, 2019...
Page 435 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of the OLSN and OLSP bits in the TOCR1A register or the OLS1N to OLS3N and OLS1P to OLS3P bits in the TOCR2A register. This initial output is the non-active level of the PWM output and continues from when complementary PWM mode is set with the MTU3.TMDR1 until MTU4.TCNT exceeds the value set in the TDDRA register.
Page 436 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Timer output control register settings TOCR1A.OLSN bit = 0 (initial output: high; active level: low) TOCR1A.OLSP bit = 0 (initial output: high; active level: low) MTU3.TCNT MTU4.TCNT MTU3.TCNT value MTU4.TCNT TCNTSA MTU3.TCNT MTU4.TCNT TDDRA...
Page 437 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Method for Generating PWM Output in Complementary PWM Mode In complementary PWM mode, six phases (three positive and three negative) PWM waveforms can be output. Dead time can be set for PWM waveforms to be output. A PWM waveform is generated by output of the level selected in the timer output control register in the event of a compare match between a counter and a compare register.
Page 438 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) T1 interval T2 interval T1 interval Counter for generating MTU3.TGRA a turn-off timing Counter for generating TEMP2 a turn-on timing TCDRA MTU4.TGRA TDDRA 0000h Positive-phase Don't care output Negative-phase output Output waveform is active-low. Buffer operation is set for transfer at the crest and trough.
Page 439 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 0% and 100% Duty Ratio Output in Complementary PWM Mode In complementary PWM mode, 0% and 100% duty PWM output can be output as required. Figure 19.56 to Figure 19.60 show output examples. A 100% duty waveform is output when the compare register value is set to 0000h.
Page 440 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) T1 interval T2 interval T1 interval Counter for generating MTU3.TGRA a turn-off timing TEMP2 Counter for generating a turn-on timing TCDRA MTU4.TGRA TDDRA 0000h 0% duty ratio output Positive-phase Don't care output 100% duty ratio output Negative-phase...
Page 441 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) T1 interval T2 interval T1 interval Counter for generating a turn-off timing MTU3.TGRA Counter for generating MTU4.TGRA a turn-on timing TCDRA MTU3.TCNT MTU4.TCNT TDDRA 0000h Don't care 0% duty ratio output Positive-phase output 100% duty ratio output...
Page 442 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (m) Counter Clearing by Another Channel In complementary PWM mode, MTU3.TCNT, MTU4.TCNT, and TCNTSA can be cleared by another channel source when a mode for synchronization with another channel is specified through the TSYRA register and synchronous clearing is selected with MTU3.TCR.CCLR[2:0] bits.
Page 443 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCRA to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval (Tb2 interval) at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing.
Page 444 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c)  Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode. An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in Figure 19.64 .
Page 445 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c)  Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figure 19.65 to Figure 19.68 show examples of output waveform control in which MTU3 and MTU4 operate in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCRA is set to 1.
Page 446 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Synchronous clearing WRE bit = 1 MTU3.TCNT MTU4.TCNT MTU3.TGRA TCNTSA TCDRA MTU3.TGRB MTU3.TCNT MTU4.TCNT TDDRA 0000h Positive- phase output Negative-phase output (Output waveform is active-low) Figure 19.67 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 19.63;...
Page 447 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (o) Counter Clearing by MTU3.TGRA Compare Match In complementary PWM mode, MTU3.TCNT, MTU4.TCNT, and TCNTSA can be cleared by MTU3.TGRA compare match when the TWCRA.CCE bit. Figure 19.69 illustrates an operation example. Note 1.
Page 448 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (p) Example of Waveform Output for Driving AC Synchronous Motor (Brushless DC Motor) In complementary PWM mode when MTU3 and MTU4 are used, a brushless DC motor can easily be controlled using the TGCRA register.
Page 449 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) UF bit TGCRA VF bit WF bit 6-phase output MTIOC3B pin MTIOC3D pin MTIOC4A pin MTIOC4C pin MTIOC4B pin MTIOC4D pin ■ When TGCRA.BDC = 1, TGCRA.N = 0, TGCRA.P = 0, TGCRA.FB = 1, and output active level = high Figure 19.72 Example of Output Phase Switching through UF, VF, and WF Bit Settings (1)
Page 450 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (q) A/D Converter Start Request Setting In complementary PWM mode, an A/D converter start request can be issued using MTU3.TGRA compare match, MTU4.TCNT underflow (trough), or compare match on a channel other than MTU3 and MTU4. When start requests using MTU3.TGRA compare match are specified, A/D conversion can be started at the crest of the MTU3.TCNT count.
Page 451 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Figure 19.75 shows an example when the buffer write value is smaller than the TDDRA value, and Figure 19.76 shows an example when the write value is greater than TCDRA. In the crest interval, the output is controlled according to the compare match with the compare register or temporary register A;...
Page 452 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (3) Interrupt Skipping Function 1 in Complementary PWM Mode Interrupts TGIA3 (at the crest) and TCIV4 (at the trough) in MTU3 and MTU4 can be skipped up to seven times by making settings in the TITCR1A register.
Page 453 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (b) Example of Interrupt Skipping Function 1 Figure 19.79 shows an example of TGIA3 interrupt skipping in which the interrupt skipping count is set to three by the T3ACOR bits and the T3AEN bit is set to 1 in the TITCR1A register. Interrupt skipping period Interrupt skipping period TGIA3 interrupt...
Page 454 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Buffer Transfer Control Linked with Interrupt Skipping In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the BTE[1:0] bits in the TBTERA register. Figure 19.80 shows an example of operation when buffer transfer is disabled (BTE[1:0] = 01b).
Page 455 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) MTU3.TCNT MTU4.TCNT (1) When the buffer register is modified within one carrier period after a TGIA3 interrupt TCNTSA TGIA3 generated TGIA3 generated MTU3. TCNT MTU4. TCNT Timing for modifying Timing for modifying the buffer register the buffer register Buffer transfer-enabled period...
Page 456 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) MTU3.TCNT MTU4.TCNT TCNTSA Skipping counter TITCNT1A.T3ACNT[2:0] bits Skipping counter TITCNT1A.T4VCNT[2:0] bits Buffer transfer-enabled period (TITCNT1A.T3AEN bit is set to 1) Buffer transfer-enabled period (TITCNT1A.T4VEN bit is set to 1) Buffer transfer-enabled period (TITCNT1A.T3AEN and T4VEN bits are set to 1) Note: The skipping count is set to three.
Page 457 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (4) Complementary PWM Mode Output Protection Functions The following output protection functions are provided for complementary PWM mode. (a) Register and Counter Miswrite Prevention Function Access from the CPU to the mode registers, control registers, compare registers, and counters can be enabled or disabled by setting the RWE bit in the TRWERA register.
Page 458: A/D Converter Start Request Delaying Function
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.9 A/D Converter Start Request Delaying Function A/D converter start requests can be issued in MTU4 by making settings in the timer A/D converter start request control register (MTU4.TADCR), timer A/D converter start request cycle set registers (MTU4.TADCORA and MTU4.TADCORB), and timer A/D converter start request cycle set buffer registers (MTU4.TADCOBRA and MTU4.TADCOBRB).
Page 459 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (2) Basic Example of A/D Converter Start Request Delaying Function Operation Figure 19.84 shows a basic example of A/D converter start request signal (TRG4AN) operation when the trough of MTU4.TCNT is specified for the buffer transfer timing and an A/D converter start request signal is output during MTU4.TCNT down-counting.
Page 460 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (4) Buffer Transfer The data in the timer A/D converter start request cycle set registers (MTU4.TADCORA and MTU4.TADCORB) is updated by writing data to the timer A/D converter start request cycle set buffer registers (MTU4.TADCOBRA and MTU4.TADCOBRB).
Page 461 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (5) A/D Converter Start Request Delaying Function Linked with Interrupt Skipping Function 1 In complementary PWM mode, A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with interrupt skipping 1 by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the MTU4.TADCR register.
Page 462 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) MTU4. TCNT MTU4.TADCORA TGIA3 interrupt skipping counter TCIV4 interrupt skipping counter TGIA3 A/D request- enabled period TCIV4 A/D request- enabled period A/D converter start request (TRG4AN) When linked with TGIA3 and TCIV4 interrupt skipping When linked with TGIA3 interrupt skipping...
Page 463 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (6) A/D Converter Start Request Delaying Function Linked with Interrupt Skipping Function 2 By setting the TITM bit to 1 in the TITMRA register, the counter starts down-counting from the value (0 to 7) set in the TRG4COR[2:0] bits in TITCR2A register every time an A/D converter start trigger (TRG4AN or TRG4BN) is generated.
Page 464: Synchronous Operation Of Mtu0 To Mtu4
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.10 Synchronous Operation of MTU0 to MTU4 (1) Synchronous Counter Start for MTU0 to MTU4 The counters in MTU0 to MTU4 can be started synchronously by making the TCSYSTR settings. (a) Example of Procedure for Setting Synchronous Counter Start for MTU0 to MTU4 Figure 19.90 shows an example of procedure for setting synchronous counter start for MTU0 to MTU4.
Page 465: External Pulse Width Measurement
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.11 External Pulse Width Measurement The pulse widths of up to three external input lines can be measured in MTU5. When the IOC[4:0] bits in MTU5.TIORU, MTU5.TIORV, MTU5.TIORW are set for pulse width measurement, the pulse width of the signal input to the MTIC5U, MTIC5V, and MTIC5W pins are measured.
Page 466: Dead Time Compensation
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.12 Dead Time Compensation A dead time delay (a propagation delay of the inverter output from the complementary PWM output) can be compensated by combining MTU5 with MTU3 and MTU4. Figure 19.94 shows an example of the motor control circuit compensating a dead time delay by combining MTU5 with MTU3 and MTU4.
Page 467 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (1) Example of Dead Time Compensation Setting Procedure Figure 19.96 shows an example of dead time compensation setting procedure by using three counters in MTU5. [1] Set MTU3 and MTU4 to complementary PWM mode. For details, refer to Complementary PWM mode section 19.3.8, Complementary PWM Mode.
Page 468: Tcntu, Tcntv, And Tcntw Capture At Crest And/Or Trough In Complementary Pwm Mode
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.13 TCNTU, TCNTV, and TCNTW Capture at Crest and/or Trough in Complementary PWM Mode The MTU5 external pulse width measurement function allows to transfer the value in TCNTU, TCNTV, and TCNTW to TGRU, TGRV, and TGRW at the crest, or trough, or crest and trough when MTU3 and MTU4 operate in complementary PWM mode.
Page 469: Noise Filter Function
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.3.14 Noise Filter Function The input capture input pins and external pulse input pins have a noise filter function. Set the NFCRn register (n = 0 to 5, C) to enable or disable the noise filter function and set the sampling clock. The noise filter for each pin can be enabled or disabled individually, and the sampling clock can be set for each channel.
Page 470: Interrupt Sources
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.4 Interrupt Sources 19.4.1 Interrupt Sources and Priorities There are three kinds of interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own enable/disable bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
Page 471: Dtc Trigger Sources
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (1) Input Capture/Compare Match Interrupt If the TIER.TGIE bit is set to 1 when a TGR input capture/compare match occurs on a channel, an interrupt is requested. The MTU has 21 input capture/compare match interrupts (six for MTU0, four each for MTU3 and MTU4, two each for MTU1 and MTU2, and three for MTU5).
Page 472: A/D Converter Trigger Sources
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.4.3 A/D Converter Trigger Sources The A/D converter can be triggered by one of the following three methods in the MTU. Table 19.63 shows the relationship between interrupt sources and A/D converter start request signals. (1) A/D Conversion Start by TGRA Input Capture/Compare Match or at Trough of MTU4.TCNT in Complementary PWM Mode The A/D converter can be triggered by the occurrence of a TGRA input capture/compare match in each channel.
Page 473 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Table 19.63 Interrupt Sources and A/D Converter Start Request Signals Target Registers Interrupt Source A/D Converter Start Request Signal MTU0.TGRA and MTU0.TCNT Input capture/compare match TRGA0N MTU1.TGRA and MTU1.TCNT TRGA1N MTU2.TGRA and MTU2.TCNT TRGA2N MTU3.TGRA and MTU3.TCNT TRGA3N...
Page 474: Operation Timing
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.5 Operation Timing 19.5.1 Input/Output Timing (1) TCNT Count Timing Figure 19.100 and Figure 19.101 show the TCNT count timing in internal clock operation, Figure 19.102 shows the TCNT count timing in external clock operation (normal mode), and Figure 19.103 shows the TCNT count timing in external clock operation (phase counting mode).
Page 475 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the value set in TIOR is output from MTIOCnm pin (n = 0 to 4;...
Page 476 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (3) Input Capture Signal Timing Figure 19.106 shows the input capture signal timing. PCLKB Input capture input Input capture signal TCNT N + 1 N + 2 N + 2 Figure 19.106 Input Capture Input Signal Timing R01UH0822EJ0100 Rev.1.00 Page 476 of 1041...
Page 477 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (4) Timing for Counter Clearing by Compare Match/Input Capture FFigure 19.107 and Figure 19.108 show the timing when counter clearing on compare match is specified, and Figure 19.109 shows the timing when counter clearing on input capture is specified. PCLKB Compare match signal Counter clear signal...
Page 478 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (5) Buffer Operation Timing Figure 19.110 to Figure 19.112 show the timing in buffer operation. PCLKB TCNT n + 1 Compare match signal TGRA, TGRB TGRC, TGRD Figure 19.110 Buffer Operation Timing (Compare Match) PCLKB Input capture signal N + 1...
Page 479 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (6) Buffer Transfer Timing (Complementary PWM Mode) Figure 19.113 to Figure 19.115 show the buffer transfer timing in complementary PWM mode. PCLKB TCNTS 0000h Buffer register write signal Temporary register transfer signal Buffer register Temporary register Figure 19.113...
Page 480: Interrupt Signal Timing
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.5.2 Interrupt Signal Timing (1) TGI Interrupt Timing by Compare Match Figure 19.116 and Figure 19.117 show the TGI interrupt request signal timing when a compare match occurs. PCLKB TCNT count clock TCNT N + 1 Compare match signal...
Page 481 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (2) TGI Interrupt Timing by Input Capture Figure 19.118 and Figure 19.119 show the TGI interrupt request signal timing when an input capture occurs. PCLKB Input capture signal TCNT Interrupt signal Figure 19.118 TGI Interrupt Timing (Input Capture) (MTU0 to MTU4) PCLKB...
Page 482 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (3) TCIV and TCIU Interrupt Timing Figure 19.120 shows the TCIV interrupt request signal timing when an overflow is generated. Figure 19.121 shows the TCIU interrupt request signal timing when an underflow is generated. PCLKB TCNT count clock TCNT (overflow)
Page 483: Usage Notes
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6 Usage Notes 19.6.1 Module Stop Function Setting MTU operation can be disabled or enabled using the module stop control register. MTU operation is stopped with the initial setting. Register access is enabled by releasing the module clock stop state. For details, refer to section 11, Low Power Consumption .
Page 484: Contention Between Tcnt Write And Clear Operations
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the TCNT write cycle, TCNT clearing takes precedence and TCNT write operation is not performed. Figure 19.123 shows the timing in this case.
Page 485: Contention Between Tgr Write Operation And Compare Match
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.6 Contention between TGR Write Operation and Compare Match If a compare match occurs in a TGR write cycle, TGR write operation is executed and the compare match signal is also generated.
Page 486: Contention Between Buffer Register Write And Tcnt Clear Operations
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.8 Contention between Buffer Register Write and TCNT Clear Operations When the buffer transfer timing is set at the TCNT clear timing by the timer buffer transfer mode register (TBTM), if TCNT clearing occurs in the TGR write cycle, the data before write operation is transferred to TGR by the buffer operation.
Page 487: Contention Between Tgr Write Operation And Input Capture
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.10 Contention between TGR Write Operation and Input Capture If an input capture signal is generated in the TGR write cycle, the input capture operation takes precedence and the TGR write operation is not performed in MTU0 to MTU4. In MTU5, the TGR write operation is performed and the input capture signal is generated.
Page 488: Contention Between Buffer Register Write Operation And Input Capture
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.11 Contention between Buffer Register Write Operation and Input Capture If an input capture signal is generated in the buffer register write cycle, the buffer operation takes precedence and the buffer register write operation is not performed. Figure 19.131 shows the timing in this case.
Page 489: Contention Between Mtu2.Tcnt Write Operation And Overflow/Underflow In Cascaded Operation
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.12 Contention between MTU2.TCNT Write Operation and Overflow/Underflow in Cascaded Operation With timer counters MTU1.TCNT and MTU2.TCNT in a cascade, when a contention occurs between MTU1.TCNT counting (an MTU2.TCNT overflow/underflow) and the MTU2.TCNT write operation, the MTU2.TCNT write operation is performed and the MTU1.TCNT count signal is disabled.
Page 490: Counter Value When Count Operation Is Stopped In Complementary Pwm Mode
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.13 Counter Value When Count Operation is Stopped in Complementary PWM Mode When counting operation in MTU3.TCNT and MTU4.TCNT is stopped in complementary PWM mode, the MTU3.TCNT value is set to the timer dead time register (TDDRA) value and MTU4.TCNT is set to 0000h. When operation is restarted in complementary PWM mode, counting begins automatically from the initial setting state.
Page 491: Buffer Operation And Compare Match In Reset-Synchronized Pwm Mode
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.15 Buffer Operation and Compare Match in Reset-Synchronized PWM Mode When setting buffer operation in reset-synchronized PWM mode, set the BFA and BFB bits in MTU4.TMDR1 to 0. The MTIOC4C pin cannot output waveforms if the BFA bit in MTU4.TMDR1 is set to 1. Likewise, the MTIOC4D pin cannot output waveforms if the BFB bit in MTU4.TMDR1 is set to 1.
Page 492: Overflow In Reset-Synchronized Pwm Mode
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.16 Overflow in Reset-Synchronized PWM Mode After reset-synchronized PWM mode is selected, MTU3.TCNT and MTU4.TCNT start counting when the CST3 bit of TSTRA is set to 1. In this state, the MTU4.TCNT count clock source and count edge are determined by the MTU3.TCR setting.
Page 493: Contention Between Overflow/Underflow And Counter Clearing
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.17 Contention between Overflow/Underflow and Counter Clearing If an overflow/underflow and counter clearing occur simultaneously, a TCIVn interrupt (n = 0 to 4) nor a TCIUn interrupt (n = 1, 2) is not generated and TCNT clearing takes precedence. Figure 19.136 shows the operation timing when a TGR compare match is specified as the clearing source and TGR is set to FFFFh.
Page 494: Note On Transition From Normal Mode Or Pwm Mode 1 To Reset-Synchronized Pwm Mode
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.19 Note on Transition from Normal Mode or PWM Mode 1 to Reset-Synchronized PWM Mode When making a transition from normal mode or PWM mode 1 to reset-synchronized PWM mode in MTU3 and MTU4, if the counter is stopped while the output pins (MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B and MTIOC4D) are held at a high level and then operation is started after a transition to reset-synchronized PWM mode, the initial pin output will not be correct.
Page 495: Interrupt Skipping Function 2
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.22 Interrupt Skipping Function 2 When interrupt skipping function 2 is in use and the difference between the values in MTU4.TADCORA and MTU4.TADCORB is small, correct counting of the number skipped may not be possible, in which case requests for A/D conversion will not be generated with the expected timing.
Page 496: Notes To Prevent Malfunctions In Synchronous Clearing For Complementary Pwm Mode
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.25 Notes to Prevent Malfunctions in Synchronous Clearing for Complementary PWM Mode If control of the output waveform is enabled (TWCRA.WRE bit = 1) at the time of synchronous counter clearing in complementary PWM mode, satisfaction of either condition 1 or 2 below has the following effects.
Page 497 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Synchronous clearing MTU3.TGRA MTU3. TCNT Tb interval Tb interval MTU4. TCNT TDDR Positive phase output Negative phase output Although there is no period for output of the active level over this Dead time is interval, synchronous clearing leads to output of the active level.
Page 498: Continuous Output Of Interrupt Signal In Response To A Compare Match
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.6.26 Continuous Output of Interrupt Signal in Response to a Compare Match When the TGR register is set to 0000h, the PCLKB/1 is set as the count clock, and compare match is set as the trigger for clearing of the count clock, the value of the TCNT counter remains 0000h, and the interrupt signal will be output continuously (i.e.
Page 499 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Write 0 to MTU4.TADCOBRA MTU4.TCNT MTU4.TADCORA MTU4.TADCOBRA A/D converter start request (TRG4AN) Complementary PWM mode An A/D converter start request is not issued during up-counting UT4AE = 1 immediately after buffer transfer (trough). DT4AE = 0 BF[1:0] = 10b (transfer at trough) UT4AE, DT4AE, BF[1:0]: Bits in TADCR...
Page 500: Mtu Output Pin Initialization
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.7 MTU Output Pin Initialization 19.7.1 Operating Modes The MTU has the following six operating modes. Waveforms can be output in any of these modes.  Normal mode (MTU0 to MTU4) ...
Page 501: Overview Of Initialization Procedures And Mode Transitions In Case Of Error During Operation
RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) 19.7.3 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation  When making a transition to a mode (Normal, PWM1, PWM2, or PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of TIOR setting.
Page 502 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) Pin initialization procedures are described below for the numbered combinations in Table 19.64 . The active level is assumed to be low. (1) Operation When Error Occurs in Normal Mode and Operation is Restarted in Normal Mode Figure 19.143 shows a case in which an error occurs in normal mode and operation is restarted in normal mode after re- setting.
Page 503 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (2) Operation When Error Occurs in Normal Mode and Operation is Restarted in PWM Mode 1 Figure 19.144 shows a case in which an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting.
Page 504 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (4) Operation When Error Occurs in Normal Mode and Operation is Restarted in Phase Counting Mode Figure 19.146 shows a case in which an error occurs in normal mode and operation is restarted in phase counting mode after re-setting.
Page 505 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (5) Operation When Error Occurs in Normal Mode and Operation is Restarted in Complementary PWM Mode Figure 19.147 shows a case in which an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
Page 506 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (6) Operation When Error Occurs in Normal Mode and Operation is Restarted in Reset- Synchronized PWM Mode Figure 19.148 shows a case in which an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 507 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (7) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Normal Mode Figure 19.149 shows a case in which an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
Page 508 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (8) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in PWM mode 1 Figure 19.150 shows a case in which an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
Page 509 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (10) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Phase Counting Mode Figure 19.152 shows a case in which an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting.
Page 510 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (11) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Complementary PWM Mode Figure 19.153 shows a case in which an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
Page 511 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (12) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Reset- Synchronized PWM Mode Figure 19.154 shows a case in which an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 512 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (13) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in Normal Mode Figure 19.155 shows a case in which an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
Page 513 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (14) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in PWM Mode 1 Figure 19.156 shows a case in which an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
Page 514 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (15) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in PWM Mode 2 Figure 19.157 shows a case in which an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting.
Page 515 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (17) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in Normal Mode Figure 19.159 shows a case in which an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
Page 516 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (18) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 1 Figure 19.160 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
Page 517 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (19) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 2 Figure 19.161 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
Page 518 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (21) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Normal Mode Figure 19.163 shows a case in which an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
Page 519 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (22) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in PWM Mode 1 Figure 19.164 shows a case in which an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 520 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (23) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Complementary PWM Mode Figure 19.165 shows a case in which an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the period and duty settings at the time of stopping the counter).
Page 521 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (24) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Complementary PWM Mode with New Settings Figure 19.166 shows a case in which an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (operation is restarted using new period and duty ratio settings).
Page 522 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (25) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Reset-Synchronized PWM Mode Figure 19.167 shows a case in which an error occurs in complementary PWM mode and operation is restarted in reset- synchronized PWM mode after re-setting.
Page 523 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (26) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Normal Mode Figure 19.168 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in normal mode after re-setting.
Page 524 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (27) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in PWM Mode 1 Figure 19.169 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 525 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (28) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Complementary PWM Mode Figure 19.170 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in complementary PWM mode after re-setting.
Page 526 RX13T Group 19. Multi-Function Timer Pulse Unit 3 (MTU3c) (29) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Reset-Synchronized PWM Mode Figure 19.171 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 527: Port Output Enable 3 (Poe3C)
RX13T Group 20. Port Output Enable 3 (POE3C) Port Output Enable 3 (POE3C) This MCU incorporates a port output enable 3 (POE3C) which can be used to, under various conditions, disable output signals for the MTU. Every output signal is put in the high-impedance state when the output is disabled. In this section, “PCLK”...
Page 528 RX13T Group 20. Port Output Enable 3 (POE3C) POECR1 to POECR5 Output-level MTIOC3B comparison circuit Input signals for use in MTIOC3D control of complementary MTIOC4A Output-level comparison circuit PWM output from the MTU MTIOC4C pins (MTU3 and MTU4) MTIOC4B Output-level comparison circuit MTIOC4D High-impedance request signal or...
Page 529 RX13T Group 20. Port Output Enable 3 (POE3C) Table 20.2 shows I/O pins to be used by the POE. Table 20.2 POE I/O Pins Pin Name Description POE0# Input Request signal to put the outputs of the MTU complementary PWM output pins (MTU3, MTU4 pins) in the high-impedance state, and is also capable of controlling the other target pins by register settings.
Page 530: Register Descriptions
RX13T Group 20. Port Output Enable 3 (POE3C) 20.2 Register Descriptions The POE registers are initialized by a reset. 20.2.1 Input Level Control/Status Register 1 (ICSR1) Address(es): POE.ICSR1 0008 C4C0h — — — POE0F — — — PIE1 — — —...
Page 531: Input Level Control/Status Register 3 (Icsr3)
RX13T Group 20. Port Output Enable 3 (POE3C) 20.2.2 Input Level Control/Status Register 3 (ICSR3) Address(es): POE.ICSR3 0008 C4C8h — — — POE8F — — POE8E PIE3 — — — — — — POE8M[1:0] Value after reset: Symbol Bit Name Description b1, b0 POE8M[1:0]...
Page 532: Input Level Control/Status Register 4 (Icsr4)
RX13T Group 20. Port Output Enable 3 (POE3C) For details, refer to section 20.3.7, Recover from High-Impedance State . 20.2.3 Input Level Control/Status Register 4 (ICSR4) Address(es): POE.ICSR4 0008 C4D6h POE10 POE10 — — — — — PIE4 — — —...
Page 533: Input Level Control/Status Register 6 (Icsr6)
RX13T Group 20. Port Output Enable 3 (POE3C) [Clearing condition]  By writing 0 to the POE10F flag after reading POE10F = 1 When low-level sampling is set by the POE10M[1:0] bits, the high level needs to be input to the POE10# pin to write 0 to this flag.
Page 534: Output Level Control/Status Register 1 (Ocsr1)
RX13T Group 20. Port Output Enable 3 (POE3C) 20.2.5 Output Level Control/Status Register 1 (OCSR1) Address(es): POE.OCSR1 0008 C4C2h OSF1 — — — — — OCE1 OIE1 — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 535: Active Level Setting Register 1 (Alr1)
RX13T Group 20. Port Output Enable 3 (POE3C) refer to section 20.3.7, Recover from High-Impedance State . 20.2.6 Active Level Setting Register 1 (ALR1) Address(es): POE.ALR1 0008 C4DAh OLSG2 OLSG2 OLSG1 OLSG1 OLSG0 OLSG0 — — — — — — —...
Page 536 RX13T Group 20. Port Output Enable 3 (POE3C) OLSG2A Bit (MTIOC4B Pin Active Level Setting) This bit sets the active level of the MTIOC4B output. Specifically, setting the OLSG2A bit to 0 sets the low level and to 1 sets the high level as the active level for detection of simultaneous conduction. OLSG2B Bit (MTIOC4D Pin Active Level Setting) This bit sets the active level of the MTIOC4D output.
Page 537: Software Port Output Enable Register (Spoer)
RX13T Group 20. Port Output Enable 3 (POE3C) 20.2.7 Software Port Output Enable Register (SPOER) Address(es): POE.SPOER 0008 C4CAh MTUC MTUC — — — — — — H0HIZ H34HIZ Value after reset: Symbol Bit Name Description MTUCH34HIZ MTU3 and MTU4 Pin High-Impedance 0: Does not put the outputs in the high-impedance Enable state.
Page 538: Port Output Enable Control Register 1 (Poecr1)
RX13T Group 20. Port Output Enable 3 (POE3C) 20.2.8 Port Output Enable Control Register 1 (POECR1) Address(es): POE.POECR1 0008 C4CBh MTU0D MTU0C MTU0B MTU0A MTU0D MTU0C MTU0B MTU0A Value after reset: Symbol Bit Name Description MTU0AZE MTIOC0A (PB3) Pin High-Impedance 0: Does not switch the pin to high-impedance state.
Page 539 RX13T Group 20. Port Output Enable 3 (POE3C) specified in the POECR5 register, the ICSRn.POEmF flag (n = 1, 4; m = 0, 10), or POECMPFR.CnFLAG flag (n = 0 to 2), is set to 1. MTU0A1ZE Bit (MTIOC0A (PD3) Pin High-Impedance Enable) This bit specifies whether to switch the MTIOC0A output of PD3 to the high-impedance state when any of the ICSR3.POE8F flag, SPOER.MTUCH0HIZ bit, and ICSR6.OSTSTF flag (when the OSTSTE bit is 1), or, as additionally specified in the POECR5 register, the ICSRn.POEmF flag (n = 1, 4;...
Page 540: Port Output Enable Control Register 2 (Poecr2)
RX13T Group 20. Port Output Enable 3 (POE3C) 20.2.9 Port Output Enable Control Register 2 (POECR2) Address(es): POE.POECR2 0008 C4CCh MTU3B MTU4A MTU4B — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b2 to b0...
Page 541: Port Output Enable Control Register 4 (Poecr4)
RX13T Group 20. Port Output Enable 3 (POE3C) 20.2.10 Port Output Enable Control Register 4 (POECR4) Address(es): POE.POECR4 0008 C4D0h IC4ADD IC3ADD CMADD — — — — — — — — — — — — — MT34ZE MT34ZE MT34ZE Value after reset: Symbol Bit Name Description...
Page 542: Port Output Enable Control Register 5 (Poecr5)
RX13T Group 20. Port Output Enable 3 (POE3C) 20.2.11 Port Output Enable Control Register 5 (POECR5) Address(es): POE.POECR5 0008 C4D2h IC4ADD IC1ADD CMADD — — — — — — — — — — — — — MT0ZE MT0ZE MT0ZE Value after reset: Symbol Bit Name Description...
Page 543: Port Output Enable Comparator Output Detection Flag Register (Poecmpfr)
RX13T Group 20. Port Output Enable 3 (POE3C) 20.2.12 Port Output Enable Comparator Output Detection Flag Register (POECMPFR) Address(es): POE.POECMPFR 0008 C4E6h C2FLA C1FLA C0FLA — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description...
Page 544: Port Output Enable Comparator Request Select Register (Poecmpsel)
RX13T Group 20. Port Output Enable 3 (POE3C) 20.2.13 Port Output Enable Comparator Request Select Register (POECMPSEL) Address(es): POE.POECMPSEL 0008 C4E8h POERE POERE POERE — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description...
Page 545: Operation
RX13T Group 20. Port Output Enable 3 (POE3C) 20.3 Operation The following shows the target pins and conditions for high-impedance control. (1) MTU3 pins (MTIOC3B, MTIOC3D) When one of the following conditions is satisfied while the POECR2.MTU3BDZE bit is 1, the pins become high- impedance.
Page 546 RX13T Group 20. Port Output Enable 3 (POE3C) When the ICSR6.OSTSTF flag becomes 1 while the ICSR6.OSTSTE bit is 1. (3) MTU4 pins (MTIOC4B, MTIOC4D) When one of the following conditions is satisfied while the POECR2.MTU4BDZE bit is 1, the pins become high- impedance.
Page 547 RX13T Group 20. Port Output Enable 3 (POE3C) impedance.  Operation for detection of the POE8# input level When the ICSR3.POE8F flag becomes 1 while the ICSR3.POE8E bit is 1.  SPOER setting When the SPOER.MTUCH0HIZ bit is set to 1. ...
Page 548 RX13T Group 20. Port Output Enable 3 (POE3C) When the ICSR1.POE0F flag becomes 1 while the POECR5.IC1ADDMT0ZE bit is 1. When the ICSR4.POE10F flag becomes 1 while the POECR5.IC4ADDMT0ZE bit and the ICSR4.POE10E bit are  Comparator output detection When the POECMPFR.C0FLAG flag becomes 1 while the POECR5.CMADDMT0ZE bit is 1 and the POECMPSEL.POEREQ0 bit is 1.
Page 549 RX13T Group 20. Port Output Enable 3 (POE3C) When the POECMPFR.C1FLAG flag becomes 1 while the POECR5.CMADDMT0ZE bit is 1 and the POECMPSEL.POEREQ1 bit is 1. When the POECMPFR.C2FLAG flag becomes 1 while the POECR5.CMADDMT0ZE bit is 1 and the POECMPSEL.POEREQ2 bit is 1.
Page 550 RX13T Group 20. Port Output Enable 3 (POE3C) OCSR1.OSF1 OCSR1.OCE1 ICSR1 POECR2 POE0# POE0F MTU3BDZE Hi-Z request signal for POECR4.IC3ADDMT34ZE MTIOC3B/MTIOC3D pin MTU4ACZE Hi-Z request signal for POECR4.IC4ADDMT34ZE MTIOC4A/MTIOC4C pin MTU4BDZE Hi-Z request signal for POECR4.CMADDMT34ZE MTIOC4B/MTIOC4D pin SPOER.MTUCH34HIZ POECR1 MTU0AZE ICSR3 Hi-Z request signal for...
Page 551: Input-Level Detection Operation
RX13T Group 20. Port Output Enable 3 (POE3C) 20.3.1 Input-Level Detection Operation If the input conditions set by ICSR1 to ICSR4 occur on the POE0#, POE8#, and POE10# pins, the outputs of the MTU complementary PWM output pins (MTU3 and MTU4 ), and MTU0 pins are in the high-impedance state. Note however, that these outputs are still in the high-impedance state even when the MTU functions are not selected for the pins.
Page 552: Output-Level Compare Operation
RX13T Group 20. Port Output Enable 3 (POE3C) (2) Low-Level Detection Figure 20.5 shows an example of operation when a pin is placed in the high-impedance state in response to low-level detection. When 16 continuous low levels are sampled with the sampling clock selected by the ICSR1 to ICSR4 registers, the low level is recognized and the outputs of the MTU complementary PWM output pins, and MTU0 pins are in the high-impedance state.
Page 553: High-Impedance Control Using Registers
RX13T Group 20. Port Output Enable 3 (POE3C) 20.3.3 High-Impedance Control Using Registers The high-impedance request of the MTU pins (MTU0, MTU3, and MTU4) can be directly controlled by using the SPOER register. For instance, setting the SPOER.MTUCH34HIZ bit to 1 switches the MTU3 and MTU4 pins specified by the POECR2 register to the high-impedance state.
Page 554 RX13T Group 20. Port Output Enable 3 (POE3C) state either by returning them to their initial state with a reset or by setting the POECMPFR.CnFLAG flag (n = 0 to 2) to When setting the POECMPFR.CnFLAG flag to 0, be sure to confirm that the analog input signal that triggered comparator output detection has returned to a normal value by performing A/D conversion and so on.
Page 555: Poe Setting Procedure
RX13T Group 20. Port Output Enable 3 (POE3C) 20.4 POE Setting Procedure Figure 20.7 shows the procedure for setting the POE. It illustrates an example of high-impedance control in response to comparison of the output levels on the MTU3 pins (MTIOC3B/MTIOC3D). In the figure, P71 is used as the MTIOC3B pin and P74 is used as the MTIOC3D pin.
Page 556: Usage Notes
RX13T Group 20. Port Output Enable 3 (POE3C) 20.6 Usage Notes 20.6.1 Transition to Low Power Consumption Mode When the POE is used, do not make a transition to software standby mode. In this mode, the POE stops and thus the high-impedance control of pins cannot operate.
Page 557: Compare Match Timer (Cmt)
RX13T Group 21. Compare Match Timer (CMT) Compare Match Timer (CMT) This MCU has an on-chip compare match timer (CMT) unit (unit 0) consisting of a two-channel 16-bit timer (i.e., a total of two channels). The CMT has a 16-bit counter, and can generate interrupts at set intervals. In this section, “PCLK”...
Page 558: Register Descriptions
RX13T Group 21. Compare Match Timer (CMT) 21.2 Register Descriptions 21.2.1 Compare Match Timer Start Register 0 (CMSTR0) Address(es): 0008 8000h — — — — — — — — — — — — — — STR1 STR0 Value after reset: Symbol Bit Name Description...
Page 559: Compare Match Counter (Cmcnt)
RX13T Group 21. Compare Match Timer (CMT) 21.2.3 Compare Match Counter (CMCNT) Address(es): CMT0.CMCNT 0008 8004h, CMT1.CMCNT 0008 800Ah Value after reset: The CMCNT counter is a readable/writable up-counter. When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTR0.STRn (n = 0, 1) bit is set to 1, the CMCNT counter starts counting up using the selected clock.
Page 560: Operation
RX13T Group 21. Compare Match Timer (CMT) 21.3 Operation 21.3.1 Periodic Count Operation When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTR0.STRn (n = 0, 1) bit is set to 1, the CMCNT counter starts counting up using the selected clock. When the value in the counter and the value in the register match, a compare match interrupt (CMIn) (n = 0,1) is generated.
Page 561: Interrupts
RX13T Group 21. Compare Match Timer (CMT) 21.4 Interrupts 21.4.1 Interrupt Sources The CMT has channels and each of them to which a different vector address is allocated has a compare match interrupt (CMIn) (n = 0, 1). When a compare match interrupt occurs, the corresponding interrupt request is output. When the interrupt request is used to generate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings.
Page 562: Usage Notes
RX13T Group 21. Compare Match Timer (CMT) 21.5 Usage Notes 21.5.1 Setting the Module Stop Function The CMT can be enabled or disabled using the module stop control register. After a reset, the CMT is in the module stop state. The registers can be accessed by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 563: Independent Watchdog Timer (Iwdta)
RX13T Group 22. Independent Watchdog Timer (IWDTa) Independent Watchdog Timer (IWDTa) In this section, “PCLK” is used to refer to PCLKB. 22.1 Overview The independent watchdog timer (IWDT) can be used to detect programs being out of control. The user can detect when a program runs out of control if an underflow occurs, by creating a program that refreshes the IWDT counter before it underflows.
Page 564 RX13T Group 22. Independent Watchdog Timer (IWDTa) To use the IWDT, the IWDT-dedicated clock (IWDTCLK) should be supplied so that the IWDT operates even if the peripheral module clock (PCLK) stops. The bus interface and registers operate with PCLK, and the 14-bit counter and control circuits operate with IWDTCLK.
Page 565: Register Descriptions
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.2 Register Descriptions 22.2.1 IWDT Refresh Register (IWDTRR) Address(es): IWDT.IWDTRR 0008 8030h Value after reset: Description b7 to b0 The counter is refreshed by writing 00h and then writing FFh to this register. The IWDTRR register refreshes the counter of the IWDT.
Page 566: Iwdt Control Register (Iwdtcr)
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.2.2 IWDT Control Register (IWDTCR) Address(es): IWDT.IWDTCR 0008 8032h — — RPSS[1:0] — — RPES[1:0] CKS[3:0] — — TOPS[1:0] Value after reset: Symbol Bit Name Description b1, b0 TOPS[1:0] Timeout Period Select b1 b0 0 0: 128 cycles (007Fh) 0 1: 512 cycles (01FFh) 1 0: 1024 cycles (03FFh)
Page 567 RX13T Group 22. Independent Watchdog Timer (IWDTa) TOPS[1:0] Bits (Timeout Period Select) These bits select the timeout period (period until the counter underflows) from among 128, 512, 1024, or 2048 cycles, taking the divided clock specified by the CKS[3:0] bits as one cycle. After the counter is refreshed, the combination of the CKS[3:0] and TOPS[1:0] bits determines the time (number of IWDTCLK cycles) until the counter underflows.
Page 568 RX13T Group 22. Independent Watchdog Timer (IWDTa) RPES[1:0] Bits (Window End Position Select) These bits select 75%, 50%, 25% or 0% of the count period for the window end position of the counter. The window end position should be a value smaller than the window start position (window start position > window end position). If the window end position is greater than the window start position, only the window start position setting is enabled.
Page 569: Iwdt Status Register (Iwdtsr)
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.2.3 IWDT Status Register (IWDTSR) Address(es): IWDT.IWDTSR 0008 8034h REFEF UNDFF CNTVAL[13:0] Value after reset: Symbol Bit Name Description b13 to b0 CNTVAL[13:0] Counter Value Value counted by the counter UNDFF Underflow Flag 0: No underflow occurred R/(W) 1: Underflow occurred...
Page 570: Iwdt Reset Control Register (Iwdtrcr)
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.2.4 IWDT Reset Control Register (IWDTRCR) Address(es): IWDT.IWDTRCR 0008 8036h RSTIR — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 0. Writing to these bits has no effect. RSTIRQS Reset Interrupt Request Select 0: Non-maskable interrupt request output is enabled.
Page 571: Iwdt Count Stop Control Register (Iwdtcstpr)
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.2.5 IWDT Count Stop Control Register (IWDTCSTPR) Address(es): IWDT.IWDTCSTPR 0008 8038h SLCST — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 0. Writing to these bits has no effect. SLCSTP Sleep Mode Count Stop Control 0: Count stop is disabled.
Page 572: Operation
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.3 Operation 22.3.1 Count Operation in Each Start Mode Select the IWDT start mode by setting the IWDTSTRT bit in option function select register 0 (OFS0). When the OFS0.IWDTSTRT bit is 1 (register start mode), the IWDTCR, IWDTRCR, and IWDTCSTPR registers are enabled, and counting is started by refresh operation (writing) to the IWDTRR register.
Page 573 RX13T Group 22. Independent Watchdog Timer (IWDTa) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin IWDTCR register (1) Initial value Writing to the Writing to the Writing to the (2) Set value register is invalid. register is valid.
Page 574: Auto-Start Mode
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.3.1.2 Auto-Start Mode When the IWDTSTRT bit in option function select register 0 (OFS0) is 0, auto-start mode is selected, and the IWDTCR, IWDTRCR, and IWDTCSTPR registers are disabled. Within the reset state, the clock divide ratio, window start and end positions, timeout period, reset output or interrupt request output, and counter stop control at transitions to low power consumption states are set using the values specified in the OFS0 register.
Page 575 RX13T Group 22. Independent Watchdog Timer (IWDTa) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin Refresh the counter (active high) Counting starts Counting starts Counting starts Counting starts Underflow Refresh error Refresh error Status flag cleared REFEF flag Status flag...
Page 576: Control Over Writing To The Iwdtcr, Iwdtrcr, And Iwdtcstpr Registers
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.3.2 Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers Writing to the IWDTCR, IWDTRCR, or IWDTCSTPR register is only possible once between the release from the reset state and the first refresh operation. After a refresh operation (counting starts) or the IWDTCR, IWDTRCR, or IWDTCSTPR register is written to, the protection signal in the IWDT becomes 1 to protect registers IWDTCR, IWDTRCR, and IWDTCSTPR against subsequent attempts at writing.
Page 577: Refresh Operation
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.3.3 Refresh Operation The counter is refreshed and starts operation (counting is started by refreshing) by writing the values 00h and then FFh to the IWDTRR register. If a value other than FFh is written after 00h, the counter is not refreshed. After such invalid writing, correct refreshing is performed by again writing 00h and then FFh to the IWDTRR register.
Page 578 RX13T Group 22. Independent Watchdog Timer (IWDTa) Figure 22.6 shows the IWDT refresh-operation waveforms when PCLK > IWDTCLK and clock divide ratio = IWDTCLK. Peripheral module clock (PCLK) IWDT-dedicated clock (IWDTCLK) Data written to IWDTRR register IWDTRR register write Valid signal (internal signal) IWDTRR register Invalid...
Page 579: Status Flags
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.3.4 Status Flags The IWDTSR.REFEF and IWDTSR.UNDFF flags retain the source of the reset signal output from the IWDT or the source of the interrupt request from the IWDT. Thus, after release from the reset state or interrupt request generation, read the IWDTSR.REFEF and IWDTSR.UNDFF flags to check for the reset or interrupt source.
Page 580: Reading The Counter Value
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.3.7 Reading the Counter Value As the counter in IWDT-dedicated clock (IWDTCLK), the counter value cannot be read directly. The IWDT synchronizes the counter value with the peripheral module clock (PCLK) and stores it in the IWDTSR.CNTVAL[13:0] bits.
Page 581: Correspondence Between Option Function Select Register 0 (Ofs0) And Iwdt Registers
RX13T Group 22. Independent Watchdog Timer (IWDTa) 22.3.8 Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers Table 22.5 lists the correspondence between option function select register 0 (OFS0) used in auto-start mode and the registers used in register start mode. Do not change the OFS0 register setting during IWDT operation.
Page 582: Serial Communications Interface (Scig, Scih)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Serial Communications Interface (SCIg, SCIh) This MCU has three independent serial communications interface (SCI) channels. The SCI consists of the SCIg module (SCI1 and SCI5) and the SCIh module (SCI12). The SCIg module (SCI1 and SCI5) can handle both asynchronous and clock synchronous serial communications. Asynchronous serial data communications can be carried out with standard asynchronous communications chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communications Interface Adapter (ACIA).
Page 583 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.1 SCIg Specifications (2/2) Item Description Clock synchronous Data length 8 bits mode Receive error detection Overrun error Hardware flow control CTSn# and RTSn# pins can be used in controlling transmission/reception. Smart card interface Error processing An error signal can be automatically transmitted when detecting a parity error during...
Page 584 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.2 SCIh Specifications (2/2) Item Description Asynchronous Data length 7, 8, or 9 bits mode Transmission stop bit 1 or 2 bits Parity Even parity, odd parity, or no parity Receive error detection Parity, overrun, and framing errors Hardware flow control CTSn# and RTSn# pins can be used in controlling transmission/reception.
Page 585 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.3 Functions of SCI Channels Item SCI1 SCI5 SCI12 Asynchronous mode Available Available Available Clock synchronous mode Available Available Available Smart card interface mode Available Available Available Simple I C mode Available Available Available...
Page 586 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) SCK12 RTS12#/CTS12#/SS12# MTIOC1A MTIOC2A Extended serial mode control section RXD12/SSCL12/ SMISO12/RXDX12 TXD12/SSDA12/ SMOSI12/TXDX12/ SIOX12 Transmit/ Controller receive SCIX0 interrupt request block SCIX1 interrupt request SCIX2 interrupt request SCIX3 interrupt request Timer RXI interrupt request TXI interrupt request TEI interrupt request ERI interrupt request...
Page 587 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.4 to Table 23.7 list the pin configuration of the SCIs for the individual modes. Table 23.4 SCI Pin Configuration in Asynchronous Mode and Clock Synchronous Mode Channel Pin Name Function SCI1 SCK1 SCI1 clock input/output...
Page 588: Register Descriptions
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2 Register Descriptions 23.2.1 Receive Shift Register (RSR) RSR is a shift register which is used to receive serial data input from the RXDn pin and converts it into parallel data. When one frame of data has been received, it is automatically transferred to the RDR register. The RSR register cannot be directly accessed by the CPU.
Page 589: Receive Data Register H, L, Hl (Rdrh, Rdrl, Rdrhl)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.3 Receive Data Register H, L, HL (RDRH, RDRL, RDRHL)  Receive Data Register H (RDRH) Address(es): SCI1.RDRH 0008 A030h, SCI5.RDRH 0008 A0B0h, SCI12.RDRH 0008 B310h  Receive Data Register L (RDRL) Address(es): SCI1.RDRL 0008 A031h, SCI5.RDRL 0008 A0B1h, SCI12.RDRL 0008 B311h ...
Page 590: Transmit Data Register H, L, Hl (Tdrh, Tdrl, Tdrhl)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.5 Transmit Data Register H, L, HL (TDRH, TDRL, TDRHL)  Transmit Data Register H (TDRH) Address(es): SCI1.TDRH 0008 A02Eh, SCI5.TDRH 0008 A0AEh, SCI12.TDRH 0008 B30Eh  Transmit Data Register L (TDRL) Address(es): SCI1.TDRL 0008 A02Fh, SCI5.TDRL 0008 A0AFh, SCI12.TDRL 0008 B30Fh ...
Page 591: Serial Mode Register (Smr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.7 Serial Mode Register (SMR) Note: Some bits in SMR have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SMR 0008 A020h, SCI5.SMR 0008 A0A0h, SCI12.SMR 0008 B300h STOP CKS[1:0] Value after reset:...
Page 592 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) STOP Bit (Stop Bit Length) Selects the stop bit length in transmission. In reception, only the first stop bit is checked regardless of this bit setting. If the second stop bit is 0, it is treated as the start bit of the next transmit frame.
Page 593 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SMR 0008 A020h, SMCI5.SMR 0008 A0A0h, SMCI12.SMR 0008 B300h BCP[1:0] CKS[1:0] Value after reset: Symbol Bit Name Description b1, b0 CKS[1:0] Clock Select R/W* b1 b0 0 0: PCLK (n = 0)*...
Page 594 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) PM Bit (Parity Mode) Selects the parity mode for transmission and reception (even or odd). For details on the usage of this bit in smart card interface mode, refer to section 23.6.2, Data Format (Except in Block Transfer Mode) .
Page 595: Serial Control Register (Scr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.8 Serial Control Register (SCR) Note: Some bits in the SCR register have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SCR 0008 A022h, SCI5.SCR 0008 A0A2h, SCI12.SCR 0008 B302h MPIE TEIE...
Page 596 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) CKE[1:0] Bits (Clock Enable) These bits select the clock source and SCKn pin function. The combination of the settings of these bits and of the SEMR.ACS0 bit sets the internal MTU clock. TEIE Bit (Transmit End Interrupt Enable) Enables or disables a TEI interrupt request.
Page 597 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SCR 0008 A022h, SMCI5.SCR 0008 A0A2h, SMCI12.SCR 0008 B302h MPIE TEIE CKE[1:0] Value after reset: Symbol Bit Name Description  When SMR.GM = 0 b1, b0 CKE[1:0] Clock Enable...
Page 598 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) RE Bit (Receive Enable) Enables or disables serial reception. When this bit is set to 1, serial reception is started by detecting the start bit. Note that the SMR register should be set prior to setting the RE bit to 1 in order to designate the reception format.
Page 599: Serial Status Register (Ssr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.9 Serial Status Register (SSR) Some bits in the SSR register have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SSR 0008 A024h, SCI5.SSR 0008 A0A4h, SCI12.SSR 0008 B304h TDRE RDRF ORER...
Page 600 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) PER Flag (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]  When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 601 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) TDRE Flag (Transmit Data Empty Flag) Indicates whether the TDR register has data to be transmitted. [Setting condition]  When data is transferred from TDR to TSR [Clearing condition]  When data is written to TDR R01UH0822EJ0100 Rev.1.00 Page 601 of 1041 Jul 31, 2019...
Page 602 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SSR 0008 A024h, SMCI5.SSR 0008 A0A4h, SMCI12.SSR 0008 B304h TDRE RDRF ORER TEND MPBT Value after reset: Symbol Bit Name Description MPBT Multi-Processor Bit Transfer This bit should be set to 0 in smart card interface mode.
Page 603 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) PER Flag (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]  When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 604: Smart Card Mode Register (Scmr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.10 Smart Card Mode Register (SCMR) Address(es): SCI1.SCMR 0008 A026h, SCI5.SCMR 0008 A0A6h, SCI12.SCMR 0008 B306h, SMCI1.SCMR 0008 A026h, SMCI5.SCMR 0008 A0A6h, SMCI12.SCMR 0008 B306h BCP2 — — CHR1 SDIR SINV — SMIF Value after reset: Symbol...
Page 605 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) BCP2 Bit (Base Clock Pulse 2) Selects the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set this bit in combination with the SMR.BCP[1:0] bits. Table 23.9 Combinations of the SCMR.BCP2 Bit and SMR.BCP[1:0] Bits SCMR.BCP2 Bit...
Page 606: Bit Rate Register (Brr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.11 Bit Rate Register (BRR) Address(es): SCI1.BRR 0008 A021h, SCI5.BRR 0008 A0A1h, SCI12.BRR 0008 B301h Value after reset: The BRR register is an 8-bit register that adjusts the bit rate. As each SCI channel has independent baud rate generator control, different bit rates can be set for each. Table 23.10 shows the relationship between the setting (N) in the BRR register and the bit rate (B) for normal asynchronous mode, multi-processor communication, clock synchronous mode, smart card interface mode, simple SPI mode, and simple I mode.
Page 607 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.12 Clock Source Settings SMR.CKS[1:0] Bit Setting Clock Source PCLK PCLK/4 PCLK/16 PCLK/64 Table 23.13 Base Clock Settings in Smart Card Interface Mode SCMR.BCP2 Bit Setting SMR.BCP[1:0] Bit Setting Base Clock Cycles for 1-bit Period 93 clock cycles 128 clock cycles 186 clock cycles...
Page 608 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.14 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency PCLK (MHz) 9.8304 12.288 Bit Rate (bps) Error (%) n Error (%) Error (%) n Error (%) n Error (%) 0.03 –0.26...
Page 609 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.15 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) SEMR Settings SEMR Settings PCLK BGDM ABCS Maximum Bit Rate PCLK BGDM ABCS Maximum Bit Rate (MHz) (bps) (MHz) (bps) 250000 17.2032 537600 500000...
Page 610 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.16 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Maximum Bit Rate (bps) PCLK (MHz) External Input Clock (MHz) SEMR.ABCS Bit = 0 SEMR.ABCS Bit = 1 2.0000 125000 250000 9.8304 2.4576 153600...
Page 611 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.18 BRR Settings for Various Bit Rates (Clock Synchronous Mode, Simple SPI Mode) Operating Frequency PCLK (MHz) Bit Rate (bps) 2.5 k 10 k 25 k 50 k 100 k 250 k 500 k —...
Page 612 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.20 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Bit Rate (bps) PCLK (MHz) Error (%) 9600 7.1424 0.00 10.00 –30.00 10.7136 –25.00 13.00 –8.99 14.2848...
Page 613 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.22 BRR Settings for Various Bit Rates (Simple I C Mode) Operating Frequency PCLK (MHz) Bit Rate (bps) Error (%) n Error (%) Error (%) n Error (%) n Error (%) 10 k –2.3 –3.8...
Page 614: Modulation Duty Register (Mddr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.12 Modulation Duty Register (MDDR) Address(es): SCI1.MDDR 0008 A032h, SCI5.MDDR 0008 A0B2h, SCI12.MDDR 0008 B312h Value after reset: The MDDR register corrects the bit rate adjusted by the BRR register. When the SEMR.BRME bit is set to 1, the bit rate generated by the on-chip baud rate generator is evenly corrected according to the settings of the MDDR register (M/256).
Page 615: Serial Extended Mode Register (Semr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Smaller settings of the SMR.CKS[1:0] bits and larger settings of the BRR register reduce difference in the length of the 1-bit period. 23.2.13 Serial Extended Mode Register (SEMR) Address(es): SCI1.SEMR 0008 A027h, SCI5.SEMR 0008 A0A7h, SCI12.SEMR 0008 B307h RXDES BGDM NFEN ABCS...
Page 616 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) ACS0 Bit (Asynchronous Mode Clock Source Select) Selects the clock source in the asynchronous mode. The ACS0 bit is valid in asynchronous mode (SMR.CM bit = 0) and when an external clock input is selected (SCR.CKE[1:0] bits = 10b or 11b).
Page 617 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) BRME Bit (Bit Rate Modulation Enable) Enables and disables the bit rate modulation function. The bit rate generated by on-chip baud rate generator is evenly corrected when this function is enabled. NFEN Bit (Digital Noise Filter Function Enable) This bit enables or disables the digital noise filter function.
Page 618: Noise Filter Setting Register (Snfr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.14 Noise Filter Setting Register (SNFR) Address(es): SCI1.SNFR 0008 A028h, SCI5.SNFR 0008 A0A8h, SCI12.SNFR 0008 B308h — — — — — NFCS[2:0] Value after reset: Symbol Bit Name Description b2 to b0 NFCS[2:0] Noise Filter Clock Select In asynchronous mode, the standard setting for the base clock is as...
Page 619: C Mode Register 1 (Simr1)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.15 C Mode Register 1 (SIMR1) Address(es): SCI1.SIMR1 0008 A029h, SCI5.SIMR1 0008 A0A9h, SCI12.SIMR1 0008 B309h IICDL[4:0] — — IICM Value after reset: Symbol Bit Name Description IICM Simple I C Mode Select R/W* SMIF IICM 0: Asynchronous mode, Multi-processor mode,...
Page 620: I 2 C Mode Register 2 (Simr2)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.16 C Mode Register 2 (SIMR2) Address(es): SCI1.SIMR2 0008 A02Ah, SCI5.SIMR2 0008 A0AAh, SCI12.SIMR2 0008 B30Ah IICACK IICCSC IICINT — — — — — Value after reset: Symbol Bit Name Description IICINTM C Interrupt Mode Select 0: Use ACK/NACK interrupts.
Page 621: I 2 C Mode Register 3 (Simr3)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.17 C Mode Register 3 (SIMR3) Address(es): SCI1.SIMR3 0008 A02Bh, SCI5.SIMR3 0008 A0ABh, SCI12.SIMR3 0008 B30Bh IICSTIF IICSTP IICRST IICSTA IICSCLS[1:0] IICSDAS[1:0] AREQ Value after reset: Symbol Bit Name Description IICSTAREQ Start Condition Generation 0: A start condition is not generated.
Page 622 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) IICRSTAREQ Bit (Restart Condition Generation) When a restart condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b as well as setting the IICRSTAREQ bit to 1. [Setting condition] ...
Page 623: C Status Register (Sisr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.18 C Status Register (SISR) Address(es): SCI1.SISR 0008 A02Ch, SCI5.SISR 0008 A0ACh, SCI12.SISR 0008 B30Ch IICACK — — — — — — — Value after reset: x: Undefined Symbol Bit Name Description IICACKR ACK Reception Data Flag 0: ACK received...
Page 624: Spi Mode Register (Spmr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.19 SPI Mode Register (SPMR) Address(es): SCI1.SPMR 0008 A02Dh, SCI5.SPMR 0008 A0ADh, SCI12.SPMR 0008 B30Dh CKPH CKPOL — — CTSE Value after reset: Symbol Bit Name Description SSn# Pin Function Enable 0: SSn# pin function is disabled. R/W* 1: SSn# pin function is enabled.
Page 625: Extended Serial Module Enable Register (Esmer)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) MFF Flag (Mode Fault Flag) This bit indicates mode fault errors. In a multi-master configuration, determine the mode fault error occurrence by reading the MFF flag. [Setting condition]  Input on the SSn# pin being at the low level during master operation in simple SPI mode (SSE bit = 1 and MSS bit = 0) [Clearing condition] ...
Page 626: Control Register 0 (Cr0)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.21 Control Register 0 (CR0) Address(es): SCI12.CR0 0008 B321h — — — — BRME RXDSF SFSF — Value after reset: Symbol Bit Name Description — Reserved This bit is read as 0. The write value should be 0. SFSF Start Frame Status Flag 0: Start Frame detection function is disabled.
Page 627: Control Register 2 (Cr2)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.23 Control Register 2 (CR2) Address(es): SCI12.CR2 0008 B323h RTS[1:0] BCCS[1:0] — DFCS[2:0] Value after reset: Symbol Bit Name Description b2 to b0 DFCS[2:0] RXDX12 Signal Digital Filter 0 0 0: Filter is disabled. Clock Select 0 0 1: Filter clock is base clock* 0 1 0: Filter clock is PCLK/8...
Page 628: Control Register 3 (Cr3)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.24 Control Register 3 (CR3) Address(es): SCI12.CR3 0008 B324h — — — — — — — SDST Value after reset: Symbol Bit Name Description SDST Start Frame Detection Start 0: Detection of Start Frame is not performed. 1: Detection of Start Frame is performed.
Page 629: Interrupt Control Register (Icr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.26 Interrupt Control Register (ICR) Address(es): SCI12.ICR 0008 B326h AEDIE BCDIE PIBDIE CF1MI CF0MI — — BFDIE Value after reset: Symbol Bit Name Description BFDIE Break Field Low Width Detected 0: Interrupts on detection of the low width for a Break Field Interrupt Enable are disabled.
Page 630: Status Register (Str)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.27 Status Register (STR) Address(es): SCI12.STR 0008 B327h — — AEDF BCDF PIBDF CF1MF CF0MF BFDF Value after reset: Symbol Bit Name Description BFDF Break Field Low Width [Setting conditions]  Detection of the low width for a Break Field Detection Flag ...
Page 631: Status Clear Register (Stcr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.28 Status Clear Register (STCR) Address(es): SCI12.STCR 0008 B328h AEDCL BCDCL PIBDC CF1MC CF0MC — — BFDCL Value after reset: Symbol Bit Name Description BFDCL BFDF Clear Setting this bit to 1 clears the STR.BFDF flag. This bit is read as 0. CF0MCL CF0MF Clear Setting this bit to 1 clears the STR.CF0MF flag.
Page 632: Control Field 0 Compare Enable Register (Cf0Cr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.30 Control Field 0 Compare Enable Register (CF0CR) Address(es): SCI12.CF0CR 0008 B32Ah CF0CE CF0CE CF0CE CF0CE CF0CE CF0CE CF0CE CF0CE Value after reset: Symbol Bit Name Description CF0CE0 Control Field 0 Bit 0 Compare Enable 0: Comparison with bit 0 of Control Field 0 is disabled.
Page 633: Secondary Control Field 1 Data Register (Scf1Dr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.33 Secondary Control Field 1 Data Register (SCF1DR) Address(es): SCI12.SCF1DR 0008 B32Dh Value after reset: PCF1DR is an 8-bit readable and writable register that holds the 8-bit secondary value for comparison with Control Field 23.2.34 Control Field 1 Compare Enable Register (CF1CR) Address(es): SCI12.CF1CR 0008 B32Eh...
Page 634: Timer Control Register (Tcr)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.36 Timer Control Register (TCR) Address(es): SCI12.TCR 0008 B330h — — — — — — — TCST Value after reset: Symbol Bit Name Description TCST Timer Count Start 0: Stops the timer counting 1: Starts the timer counting b7 to b1 —...
Page 635: Timer Prescaler Register (Tpre)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.2.38 Timer Prescaler Register (TPRE) Address(es): SCI12.TPRE 0008 B332h Value after reset: TPRE consists of an 8-bit reload register, a read buffer, and a counter, each of which has FFh as its initial value. The counter counts down in synchronization with the counter clock selected by the TMR.TCSS[2:0] bits, and is reloaded with the value in the reload register when it underflows.
Page 636: Operation In Asynchronous Mode
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.3 Operation in Asynchronous Mode Figure 23.4 shows the general format for asynchronous serial communications. One frame consists of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). In asynchronous serial communications, the communications line is usually held in the mark state (high level).
Page 637 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Table 23.27 Serial Transfer Formats (Asynchronous Mode) SCMR Setting SMR Setting Serial Transfer Format and Frame Length CHR1 STOP 9-bit data STOP 9-bit data STOP STOP 9-bit data STOP 9-bit data STOP STOP 8-bit data STOP 8-bit data...
Page 638: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times * the bit rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse * of the base clock, data is latched at the middle of each bit, as shown in Figure 23.5 .
Page 639: Clock
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.3.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be selected as the SCI’s transfer clock, according to the setting of the CM bit in the SMR register and the CKE[1:0] bits in the SCR register.
Page 640: Cts And Rts Functions
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.3.5 CTS and RTS Functions The CTS function is the use of input on the CTSn# pin in transmission control. Setting the SPMR.CTSE bit to 1 enables the CTS function. When the CTS function is enabled, placing the low level on the CTSn# pin causes transmission to start.
Page 641: Sci Initialization (Asynchronous Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.3.6 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, start by writing the initial value 00h to the SCR register and then continue through the procedure for SCI given in Figure 23.7 . Whenever the operating mode or transfer format is changed, the SCR register must be initialized before the change is made.
Page 642 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Figure 23.8 shows an example of data transmission when the SCI is set to asynchronous mode according to the flow described in Figure 23.7 after a reset. When the pin function is set to the TXD pin, it is still high-impedance because the SCR.TE bit is 0.
Page 643: Serial Data Transmission (Asynchronous Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.3.7 Serial Data Transmission (Asynchronous Mode) Figure 23.9 to Figure 23.11 show an example of the operation for serial transmission in asynchronous mode. In serial transmission, the SCI operates as described below. 1.
Page 644 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Data Start bit Parity bit Stop bit D0 D1 D7 0/1 1 D7 0/1 SCR.TE bit 1 frame TXI interrupt flag (IRn in ICU SSR.TEND flag TXI interrupt request Data written to TDR in TXI interrupt Data written to TDR in Data written to TDR in...
Page 645 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Data Start bit Parity bit Stop bit Idle state 0 D0 D7 0/1 1 0 D0 D1 D7 0/1 1 0 D0 D7 0/1 (mark state) SCR.TE bit (TIE = 1) TXI interrupt flag (IRn in ICU (TIE = 0) SSR.TEND flag...
Page 646 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) [ 1 ] SCI initialization: [ 1 ] Initialization Set data transmission. After the TE bit in SCR is set to 1, high is output for a frame, Start data transmission and transmission is enabled. [ 2 ] Transmit data write to TDR by a TXI interrupt request: When transmit data is transferred from TDR to TSR, a transmit...
Page 647: Serial Data Reception (Asynchronous Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.3.8 Serial Data Reception (Asynchronous Mode) Figure 23.13 and Figure 23.14 show an example of the operation for serial data reception in asynchronous mode. In serial data reception, the SCI operates as described below. 1.
Page 648 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Data Data Parity Stop Parity Stop Data Start bit Start bit Start bit Idle state (mark state) RXI interrupt flag (IRn in ICU* SSR.FER flag RDR data read in RXI interrupt RXI interrupt handling routine request generated...
Page 649 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) [ 1 ] Initialization [ 1 ] SCI initialization: Set data reception. Start data reception [ 2 ] [ 3 ] Receive error processing and break detection: If a receive error occurs, an ERI interrupt is generated.
Page 650 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) [ 3 ] Error processing SSR.ORER flag = 1 Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR. In combination with step [ 7 ], this will make correct reception of the next frame possible.
Page 651: Multi-Processor Communications Function
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.4 Multi-Processor Communications Function Using the multi-processor communication functions enables to transmit and receive data by sharing a communication line between multiple processors by using asynchronous serial communication in which the multi-processor bit is added. In multi-processor communication, a unique ID code is allocated to each receiving station.
Page 652: Multi-Processor Serial Data Transmission
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.4.1 Multi-Processor Serial Data Transmission Figure 23.18 is a sample flowchart of multi-processor data transmission. In the ID transmission cycle, the ID should be transmitted with the SSR.MPBT bit set to 1. In the data transmission cycle, the data should be transmitted with the MPBT bit set to 0.
Page 653: Multi-Processor Serial Data Reception
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.4.2 Multi-Processor Serial Data Reception Figure 23.20 and Figure 23.21 are sample flowcharts of multi-processor data reception. When the SCR.MPIE bit is set to 1, reading the communication data is skipped until reception of the communication data in which the multi-processor bit is set to 1.
Page 654 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Initialization [ 1 ] [ 1 ] SCI initialization: Set data reception. Start data reception [ 2 ] ID reception cycle: Set the MPIE bit in SCR to 1 and wait for ID reception.
Page 655 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) [ 5 ] Error processing SSR.ORER flag = 1 Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR. In combination with step [ 7 ], this will make correct reception of the next frame possible.
Page 656: Operation In Clock Synchronous Mode
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.5 Operation in Clock Synchronous Mode Figure 23.22 shows the data format for clock synchronous serial data communications. In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data.
Page 657: Cts And Rts Functions
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.5.2 CTS and RTS Functions In the CTS function, CTSn# pin input is used to control reception/transmission start when the clock source is the internal clock. Setting the SPMR.CTSE bit to 1 enables the CTS function. When the CTS function is enabled, placing the low level on the CTSn# pin causes reception/transmission to start.
Page 658: Sci Initialization (Clock Synchronous Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.5.3 SCI Initialization (Clock Synchronous Mode) Before transmitting and receiving data, start by writing the initial value 00h to the SCR register and then continue through the procedure for SCI given in Figure 23.23 . Whenever the operating mode or transfer format is changed, the SCR register must be initialized before the change is made.
Page 659: Serial Data Transmission (Clock Synchronous Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.5.4 Serial Data Transmission (Clock Synchronous Mode) Figure 23.24 , Figure 23.25 , and Figure 23.26 show an example of the operation for serial transmission in clock synchronous mode. In serial data transmission, the SCI operates as described below. 1.
Page 660 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Synchronization clock Serial data Bit 0 Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 SCR.TE bit TXI interrupt flag (IRn in ICU SSR.TEND flag TXI interrupt request TXI interrupt TXI interrupt TXI interrupt generated...
Page 661 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Synchronization clock Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Serial data (TIE = 1) TXI interrupt flag (IRn in ICU* (TIE = 0) SSR.TEND flag TEI interrupt TXI interrupt...
Page 662 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) [ 1 ] SCI initialization: [ 1 ] Initialization Set data transmission. [ 2 ] Writing transmit data write to TDR by a TXI interrupt Start transmission request: When transmit data is transferred from TDR to TSR, a transmit data empty interrupt (TXI) request is [ 2 ] generated.
Page 663: Serial Data Reception (Clock Synchronous Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.5.5 Serial Data Reception (Clock Synchronous Mode) Figure 23.28 and Figure 23.29 show an example of SCI operation for serial reception in clock synchronous mode. In serial data reception, the SCI operates as described below. 1.
Page 664 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Synchronization clock Serial data Bit 6 Bit 7 Bit 0 Bit 7 Bit 0 RXI interrupt flag (IRn in ICU* SSR.ORER flag RXI interrupt RXI interrupt RDR data read in RXI RDR data read in RXI request request interrupt handling routine...
Page 665 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Figure 23.30 shows a sample flowchart for serial data reception. [ 1 ] SCI initialization: Initialization [ 1 ] Make input port-pin settings for pins to be used as RXDn pins. Start data reception [ 2 ] [ 3 ] Receive error processing: If a receive error occurs, read the ORER flag in...
Page 666: Simultaneous Serial Data Transmission And Reception (Clock Synchronous Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.5.6 Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode) Figure 23.31 shows a sample flowchart for simultaneous serial transmit and receive operations in clock synchronous mode. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Page 667: Operation In Smart Card Interface Mode
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.6 Operation in Smart Card Interface Mode The SCI supports smart card (IC card) interfaces conforming to ISO/IEC 7816-3 (standard for Identification Cards), as an extended function of the SCI. Smart card interface mode can be selected using the appropriate register. 23.6.1 Sample Connection Figure 23.32 shows a sample connection between a smart card (IC card) and this MCU.
Page 668: Data Format (Except In Block Transfer Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.6.2 Data Format (Except in Block Transfer Mode) Figure 23.33 shows the data transfer formats in smart card interface mode.  One frame consists of 8-bit data and a parity bit in asynchronous mode. ...
Page 669: Block Transfer Mode
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) For communications with IC cards of the direct convention type and inverse convention type, follow the procedure below. (1) Direct Convention Type For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB first as the start character, as shown in Figure 23.34 .
Page 670: Receive Data Sampling Timing And Reception Margin
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.6.4 Receive Data Sampling Timing and Reception Margin Only the base clock generated by the on-chip baud rate generator can be used as a transmit/receive clock in smart card interface mode. In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate according to the settings of the SCMR.BCP2 bit and the SMR.BCP[1:0] bits.
Page 671: Sci Initialization (Smart Card Interface Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.6.5 SCI Initialization (Smart Card Interface Mode) Initialize the SCI following the example of flowchart shown in Figure 23.37 . Initialize the SCR and SSR registers before switching from transmit mode to receive mode and vice versa. When not changing the bit rate, it is not necessary to set the CKE[1:0] bits to 00b.
Page 672 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Figure 23.38 shows an example of data transmission when the SCI is set to smart card interface mode according to the flow described in Figure 23.37 after a reset. When the pin functions are set to the SCK and TXD pins, they are still high-impedance because the SCR.CKE[0] and SCR.TE bits are 0.
Page 673: Serial Data Transmission (Except In Block Transfer Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.6.6 Serial Data Transmission (Except in Block Transfer Mode) Serial data transmission in smart card interface mode (except in block transfer mode), in that an error signal is sampled and data can be retransmitted, is different from that in non-smart card interface mode. Figure 23.39 shows the data retransmit operation during transmission.
Page 674 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Figure 23.40 shows a sample flowchart of serial transmission. Start Initialization Start data transmission SSR.ERS flag = 0? Error processing TXI interrupt Write transmit data to TDR All transmit data written? SSR.ERS flag = 0? Error processing TXI interrupt Set bits TIE, RIE, and TE...
Page 675 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) When transmitting/receiving data using the DTC, be sure to make settings to enable the DTC before making SCI settings. For DTC settings, refer to section 16, Data Transfer Controller (DTCb) . Note that the SSR.TEND flag is set in different timings depending on the GM bit setting in the SMR register. Figure 23.41 shows the TEND flag generation timing.
Page 676: Serial Data Reception (Except In Block Transfer Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.6.7 Serial Data Reception (Except in Block Transfer Mode) Serial data reception in smart card interface mode is similar to that in non-smart card interface mode. Figure 23.42 shows the data retransmit operation in receive mode. (n + 1)-th transmitted frame nth transmitted frame...
Page 677 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Figure 23.43 shows a sample flowchart for serial data reception. Start Initialization Start data reception SSR.ORER = 0 and SSR.PER = 0? Error processing RXI interrupt Read data from RDR All data received? Set bits RIE and RE in SCR to 0 Figure 23.43...
Page 678: Clock Output Control
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.6.8 Clock Output Control Clock output can be fixed to high or low using the SCR.CKE[1:0] bits when the SMR.GM bit is 1. When the CKE[1:0] bits are set to 01b (clock output), the base clock is output from the SCK pin. For the settings of the base clock frequency (bit rate), refer to section 23.2.11, Bit Rate Register (BRR) .
Page 679: Operation In Simple I C Mode
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.7 Operation in Simple I C Mode Simple I C-bus format is composed of 8 data bits and an acknowledge bit. By continuing into a slave-address frame after a start condition or restart condition, a master device is able to specify a slave device as the partner for communications. The currently specified slave device remains valid until a new slave device is specified or a stop condition is satisfied.
Page 680: Generation Of Start, Restart, And Stop Conditions
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.7.1 Generation of Start, Restart, and Stop Conditions Writing 1 to the IICSTAREQ bit in the SIMR3 register causes the generation of a start condition. The generation of a start condition proceeds through the following operations. ...
Page 681 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Figure 23.47 shows the timing of operations in the generation of start, restart, and stop conditions. SSCLn SSDAn SIMR3.IICSTAREQ SIMR3.IICRSTAREQ SIMR3.IICSTPREQ SIMR3.IICSDAS[1:0] 11b 01b SIMR3.IICSCLS[1:0] Restart-condition generated Stop-condition generated Start-condition generated interrupt request interrupt request interrupt request Figure 23.47...
Page 682: Clock Synchronization
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.7.2 Clock Synchronization The SSCLn line may be placed at the low level in the case of a wait inserted by a slave device as the other side of transfer. Setting the IICCSC bit in the SIMR2 register to 1 applies control to obtain synchronization when the levels of the internal SSCLn clock signal and the level being input on the SSCLn pin differ.
Page 683: Ssda Output Delay
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.7.3 SSDA Output Delay The IICDL[4:0] bits in the SIMR1 register can be used to set a delay for output on the SSDAn pin relative to falling edges of output on the SSCLn pin. Delay-time settings from 0 to 31 are selectable, representing periods of the corresponding numbers of cycles of the clock signal from the on-chip baud rate generator (derived by frequency-dividing the base clock, PCLK, by the divisor selected by the CKS[1:0] bits in the SMR register).
Page 684: Sci Initialization (Simple I 2 C Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.7.4 SCI Initialization (Simple I C Mode) Before transferring data, write the initial value (00h) to SCR and initialize the interface following the example shown in Figure 23.50 . When changing the operating mode, transfer format, and so on, be sure to set SCR to its initial value before proceeding with the changes.
Page 685: Operation In Master Transmission (Simple I 2 C Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.7.5 Operation in Master Transmission (Simple I C Mode) Figure 23.51 and Figure 23.52 show examples of operations in master transmission and Figure 23.53 is a flowchart showing the procedure for data transmission. Refer to Table 23.33 for more information on the STI interrupt. When 10-bit slave addresses are in use, steps [3] and [4] in Figure 23.53 are repeated twice.
Page 686 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) [ 1 ] Initialization for simple I C mode Initialization [ 1 ] For transmission, set the SCR.RIE bit to 0 (RXI and ERI interrupts requests are disabled) Start of transmission [ 2 ] Generate a start condition.
Page 687: Master Reception (Simple I 2 C Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.7.6 Master Reception (Simple I C Mode) Figure 23.54 shows an example of operations in simple I C mode master reception and Figure 23.55 is a flowchart showing the procedure for master reception. The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts).
Page 688 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Initialization [ 1 ] [ 1 ] Initialization for simple I C mode: Set the RIE bit in SCR to 0. Start of reception [ 2 ] Generate a start condition. [ 3 ] Writing to TDR: Simultaneously set the SIMR3.IICSTAREQ bit Writing the slave address and value for the R/W bit to...
Page 689: Recovery From Bus Hang-Up
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.7.7 Recovery from Bus Hang-up If the bus is stuck by an abnormal state in SCI because of the communication error, reset the SCI according to the following steps and release the bus. (1) Set the SCR.TE and RE bit to 0 at the same time to reset SCI.
Page 690: Operation In Simple Spi Mode
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.8 Operation in Simple SPI Mode As an extended function, the SCI supports a simple SPI mode that handles transfer among one or multiple master devices and multiple slave devices. Making the settings for clock synchronous mode (SCMR.SMIF = 0, SIMR1.IICM = 0, SMR.CM = 1) plus setting the SSE bit in the SPMR to 1 places the SCI in simple SPI mode.
Page 691: States Of Pins In Master And Slave Modes
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.8.1 States of Pins in Master and Slave Modes The direction (input or output) of pins for the simple SPI mode interface differs according to whether the device is a master (SCR.CKE[1:0] = 00b or 01b and SPMR.MSS = 0) or slave (SCR.CKE[1:0] = 10b or 11b and SPMR.MSS = 1). Table 23.29 lists the states of pins according to the mode and the level on the SSn# pin.
Page 692: Relationship Between Clock And Transmit/Receive Data
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.8.4 Relationship between Clock and Transmit/Receive Data The CKPOL and CKPH bits in the SPMR can be used to set up the clock for use in transmission and reception in four different ways. The relation between the clock signal and the transmission and reception of data is shown in Figure 23.57 .
Page 693: Sci Initialization (Simple Spi Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.8.5 SCI Initialization (Simple SPI Mode) The procedure is the same as for initialization in clock synchronous mode Figure 23.23 , Sample SCI Initialization Flowchart. The CKPOL and CKPH bits in the SPMR must be set to ensure that the kind of clock signal they select is suitable for both master and slave devices.
Page 694: 23.10 Extended Serial Mode Control Section: Description Of Operation
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.10 Extended Serial Mode Control Section: Description of Operation 23.10.1 Serial Transfer Protocol The extended serial mode control section of the SCI12 can realize the serial transfer protocol composed of Start Frames and Information Frames that is shown in Figure 23.59 .
Page 695: Transmitting A Start Frame
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.10.2 Transmitting a Start Frame Figure 23.60 shows an example of operations to transmit a Start Frame, which is composed of the Break Field low width, Control Field 0, and Control Field 1. Figure 23.61 and Figure 23.62 are flowcharts for the transmission of a Start Frame.
Page 696 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Start Set 1 to ESMER.ESME Enable the extended serial mode control section. Set CR2.RTS[1:0], BCCS[1:0], and Set the timing of sampling for RXDX12 reception, clock for bus collision detection, DFCS[2:0] and sampling clock for the RXDX12 signal’s digital filter. Set PCR.SHARPS, RXDXPS, and Set the RXDX12 and TXDX12 pins.
Page 697 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Set 1 to TCR.TCST Start the timer counter and output of the Break Field low width. The STR.BFDF flag is set to 1 on output of the Break Field low width. At this time, if the ICR.BFDIE bit is 1, an SCIX0 interrupt is generated.
Page 698: Receiving A Start Frame
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.10.3 Receiving a Start Frame The extended serial mode control section is capable of receiving Start Frames with the structures listed in Table 23.30 . Table 23.30 Structures of Start Frames Bit Setting Structures of Start Frames CF0RE Information Frame...
Page 699 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Start Frame Information Frame Break Field low width Control Field 0 Control Field 1 Data Field RXDX12 pin 8 bits 8 bits Write 1 to Set to 0 after Break Field CR3.SDST low width detection CR0.RXDSF Specified period for...
Page 700 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Start Set 1 to ESMER.ESME Enable the extended serial mode control section. Set whether to include the Break Field and Control Field 0 Set CR1.BFE and CF0RE in the Start Frame. Select the data for comparison with Control Field 1 and the Set CR1.CF1DS[1:0] and PIBE presence or absence of a priority interrupt bit.
Page 701 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Start the timer counter so that determining the Set 1 to TCR.TCST Break Field is possible. Set 1 to CR3.SDST Begin detection of the Start Frame. The STR.BFDF flag is set to 1 on detection of the Break Field low width.
Page 702 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Initialization CR3.SDST = 1 Break Field [Break Field low width] detected Non-match Control Field 0 CR3.SDST = 1 [CF0RR] matches [CF0DR] Non-match Control Field 1 [CF1RR] matches [PCF1DR, SCF1DR], or both the priority interrupt bit is detected. Information Frame Figure 23.66 State Transitions When Receiving a Start Frame...
Page 703: Priority Interrupt Bit
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.10.3.1 Priority Interrupt Bit Figure 23.67 shows an example of operation in Start Frame reception where a priority interrupt bit is in use. Setting the CR1.PIBE bit to 1 enables the use of a priority interrupt bit. Operations of the extended serial mode control section in start Frame reception where a priority interrupt bit is in use are as described below.
Page 704: Detection Of Bus Collisions
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.10.4 Detection of Bus Collisions Detection of bus collisions operate for cases where output of the Break Field low width and transmission of data are in progress when the ESMER.ESME bit and the SCI.TE bit are set to 1. Figure 23.68 shows an example of operations with bus collision detection.
Page 705: Digital Filter For Input On The Rxdx12 Pin
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.10.5 Digital Filter for Input on the RXDX12 Pin Signals input through the RXDX12 pin can be passed through a digital filter before they are conveyed to the internal circuits. The digital filter consists of three flip-flop circuit stages connected in series and a match-detecting circuit. The CR2.DFCS[2:0] bits select the sampling clock for the RXDX12 pin input signals.
Page 706: Bit Rate Measurement
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.10.6 Bit Rate Measurement The bit rate measurement function measures the intervals between rising and falling edges and between falling and rising edges of the signal input from the RXDX12 pin. Figure 23.70 shows an example of operations for bit rate measurement. (1) Writing 1 to the CR0.BRME bit enables bit rate measurement.
Page 707: Selectable Timing For Sampling Data Received Through Rxdx12
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.10.7 Selectable Timing for Sampling Data Received through RXDX12 The extended serial mode control section provides a way of adjusting the timing for the sampling of data received through the RXDX12 pin by setting the CR2.RTS[1:0] bits to select the rising edges of 8th, 10th, 12th, or 14th cycle of the base clock.
Page 708: Timer
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.10.8 Timer The timer has the following operating modes. (1) Break Field Low Width Output Mode This mode is for output through the TXDX12 pin of the low level over the Break Field low width at the transmission of a Start Frame.
Page 709 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) (2) Break Field Low Width Determination Mode This mode is for determining the Break Field low width in the input signal on the RXDX12 pin at the reception of a Start Frame. Setting the TMR.TOMS[1:0] bits to 01b switches operation to Break Field low width determination mode. The TMR.TCSS[2:0] bits select the clock source for the counter.
Page 710: 23.11 Noise Cancellation Function
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.11 Noise Cancellation Function Figure 23.74 shows the configuration of the noise filter used for noise cancellation. The noise filter consists of two stages of flip-flop circuits and a match-detection circuit. When the level on the pin matches in three consecutive samples taken at the set sampling interval, the matching level continues to be conveyed internally until the level on the pin again matches in three consecutive samples.
Page 711: 23.12 Interrupt Sources
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.12 Interrupt Sources 23.12.1 Buffer Operations for TXI and RXI Interrupts If the conditions for a TXI and RXI interrupt are satisfied while the interrupt status flag in the interrupt controller is 1, the SCI does not output the interrupt request but retains it internally (with a capacity for retention of one request per source).
Page 712: Interrupts In Smart Card Interface Mode
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.12.3 Interrupts in Smart Card Interface Mode Table 23.32 lists interrupt sources in smart card interface mode. A transmit end interrupt (TEI) request cannot be used in this mode. Table 23.32 SCI Interrupt Sources Name Interrupt Source Interrupt Flag...
Page 713: Interrupts In Simple I C Mode
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.12.4 Interrupts in Simple I C Mode The interrupt sources in simple I C mode are listed in Table 23.33 . The STI interrupt is allocated to the transmit end interrupt (TEI) request. The receive error interrupt (ERI) request cannot be used. The DTC can also be used to handle transfer in simple I C mode.
Page 714: Interrupt Requests From The Extended Serial Mode Control Section
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.12.5 Interrupt Requests from the Extended Serial Mode Control Section The extended serial mode control section has a total of six types of interrupt request for generating the SCIX0 interrupt (Break Field low width detected), SCIX1 interrupt (Control Field 0 match, Control Field 1 match, priority interrupt bit detected), SCIX2 interrupt (bus collision detected), and SCIX3 interrupt (valid edge detected).
Page 715: 23.13 Usage Notes
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.13 Usage Notes 23.13.1 Setting the Module Stop Function Module stop control register B (MSTPCRB) is used to stop and start SCI operations. With the value after a reset, SCI operations are stopped. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 716: Restrictions On Clock Synchronous Transmission (Clock Synchronous Mode And Simple Spi Mode)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.13.6 Restrictions on Clock Synchronous Transmission (Clock Synchronous Mode and Simple SPI Mode) When the external clock source is used as a synchronization clock, the following restrictions apply. (1) Start of transmission Update TDR by the CPU or DTC and wait for at least five PCLK cycles before allowing the transmit clock to be input (refer to Figure 23.75 ).
Page 717: Restrictions On Using Dtc
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.13.7 Restrictions on Using DTC When using the DTC to read RDR, RDRH, and RDRL, be sure to set the receive data full interrupt (RXI) as the activation source of the relevant SCI. 23.13.8 Notes on Starting Transfer At the point where transfer starts when the interrupt status flag (IRn.IR flag) in the interrupt controller is 1, follow the...
Page 718 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Data transmission [ 1 ] Data being transmitted is lost halfway. Data can be [ 1 ] All data transmitted? normally transmitted from the CPU by setting the TE bit in SCR to 1, reading SSR, and writing data to TDR after canceling software standby mode.
Page 719 RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Transition to software standby Software standby mode mode canceled Port mode register (PMR) setting SCR.TE The level at transition to software standby mode is retained SCKn output pin TXDn output pin The level before transition to Port input/output High output Stop...
Page 720: External Clock Input In Clock Synchronous Mode And Simple Spi Mode
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) Data reception [ 1 ] Data being received is invalid. [ 1 ] RXI interrupt Read receive data in RDR SCR.RE = 0 Make transition to software standby mode [ 2 ] Setting for the module stop state is included. [ 2 ] Cancel software standby mode Change operating mode?
Page 721: Limitations On Simple Spi Mode
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.13.11 Limitations on Simple SPI Mode (1) Master Mode  Use a resistor to pull up or pull down the clock line matching the initial settings for the transfer clock set by the SPMR.CKPH and CKPOL bits when the SPMR.SSE bit is 1.
Page 722: Limitation 1 On Usage Of The Extended Serial Mode Control Section
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.13.12 Limitation 1 on Usage of the Extended Serial Mode Control Section When the PCR.SHARPS bit is set to 1, output on the TXDX12/RXDX12 pin is only possible when the following conditions apply. ...
Page 723: Note On Transmit Enable Bit (Te Bit)
RX13T Group 23. Serial Communications Interface (SCIg, SCIh) 23.13.14 Note on Transmit Enable Bit (TE Bit) When setting the pin function to “TXDn” while the SCR.TE bit is 0 (serial transmission is disabled) or setting the TE bit to 0 while the pin function is “TXDn”, output of the TXDn pin becomes high-impedance. Prevent the TXDn line from becoming high-impedance by any of the following ways: (1) Connect a pull-up resistor to the TXDn line.
Page 724: I 2 C-Bus Interface (Riica)
RX13T Group 24. I C-bus Interface (RIICa) C-bus Interface (RIICa) This MCU has a single-channel I C-bus interface (RIIC). The RIIC module conforms with the NXP I C-bus (Inter-IC bus) interface and provides a subset of its functions. In this section, “PCLK” is used to refer to PCLKB. 24.1 Overview Table 24.1 lists the specifications of the RIIC, Figure 24.1 shows a block diagram of the RIIC, and Figure 24.2 shows...
Page 725 RX13T Group 24. I C-bus Interface (RIICa) Table 24.1 RIIC Specifications (2/2) Item Description Low power consumption Module stop state can be set. function  Four RIIC operating modes Master transmit mode, master receive mode, slave transmit mode, and slave receive mode PCLK CKS[2:0] ICMR1...
Page 726 RX13T Group 24. I C-bus Interface (RIICa) Power supply for pull-up (VCC to 5 V) SCLin SCLout# SDAin SDAout# (Master) SCLin SCLin SCLout# SCLout# SDAin SDAin SDAout# SDAout# (Slave 1) (Slave 2) Figure 24.2 I/O Pin Connection to the External Circuit (I C-bus Configuration Example) The input level of the signals for RIIC is CMOS when I C-bus is selected (ICMR3.SMBS bit is 0), or TTL when SMBus...
Page 727: Register Descriptions
RX13T Group 24. I C-bus Interface (RIICa) 24.2 Register Descriptions 24.2.1 C-bus Control Register 1 (ICCR1) Address(es): RIIC0.ICCR1 0008 8300h IICRST SOWP SCLO SDAO SCLI SDAI Value after reset: Symbol Bit Name Description SDAI SDA Line Monitor 0: SDA0 line is low. 1: SDA0 line is high.
Page 728 RX13T Group 24. I C-bus Interface (RIICa) CLO Bit (Extra SCL Clock Cycle Output) This bit is used to output an extra SCL clock cycle for debugging or error processing. Normally, set the bit to 0. Setting the bit to 1 in a normal communication state causes a communication error. For details on this function, refer to section 24.11.2, Extra SCL Clock Cycle Output Function .
Page 729: C-Bus Control Register 2 (Iccr2)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.2 C-bus Control Register 2 (ICCR2) Address(es): RIIC0.ICCR2 0008 8301h BBSY — — Value after reset: Symbol Bit Name Description — Reserved This bit is read as 0. The write value should be 0. Start Condition Issuance 0: Does not request to issue a start condition.
Page 730 RX13T Group 24. I C-bus Interface (RIICa) RS Bit (Restart Condition Issuance Request) This bit is used to request that a restart condition be issued in master mode. When this bit is set to 1 to request to issue a restart condition, a restart condition is issued when the BBSY flag is set to 1 (bus busy state) and the MST bit is set to 1 (master mode).
Page 731 RX13T Group 24. I C-bus Interface (RIICa) TRS Bit (Transmit/Receive Mode) This bit indicates transmit or receive mode. The RIIC is in receive mode when the TRS bit is set to 0 and is in transmit mode when the bit is set to 1. Combination of this bit and the MST bit indicates the operating mode of the RIIC.
Page 732 RX13T Group 24. I C-bus Interface (RIICa) BBSY Flag (Bus Busy Detection Flag) The BBSY flag indicates whether the I C-bus is occupied (bus busy state) or released (bus free state). This bit is set to 1 when the SDA0 line changes from high to low under the condition of SCL0 line = high, assuming that a start condition has been issued.
Page 733: I 2 C-Bus Mode Register 1 (Icmr1)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.3 C-bus Mode Register 1 (ICMR1) Address(es): RIIC0.ICMR1 0008 8302h MTWP CKS[2:0] BCWP BC[2:0] Value after reset: Symbol Bit Name Description b2 to b0 BC[2:0] Bit Counter R/W* 0 0 0: 9 bits 0 0 1: 2 bits 0 1 0: 3 bits 0 1 1: 4 bits...
Page 734: I 2 C-Bus Mode Register 2 (Icmr2)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.4 C-bus Mode Register 2 (ICMR2) Address(es): RIIC0.ICMR2 0008 8303h DLCS SDDL[2:0] — TMOH TMOL TMOS Value after reset: Symbol Bit Name Description TMOS Timeout Detection Time Select 0: Long mode is selected. 1: Short mode is selected.
Page 735 RX13T Group 24. I C-bus Interface (RIICa) TMOH Bit (Timeout H Count Control) This bit is used to enable or disable the internal counter of the timeout function to count up while the SCL0 line is held high when the timeout function is enabled (ICFER.TMOE bit is 1). SDDL[2:0] Bits (SDA Output Delay Counter) The SDA output can be delayed by the SDDL[2:0] setting.
Page 736: I 2 C-Bus Mode Register 3 (Icmr3)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.5 C-bus Mode Register 3 (ICMR3) Address(es): RIIC0.ICMR3 0008 8304h WAIT RDRFS ACKW SMBS ACKBT ACKBR NF[1:0] Value after reset: Symbol Bit Name Description b1, b0 NF[1:0] Noise Filter Stage Select b1 b0 0 0: Noise of up to one IICφ...
Page 737 RX13T Group 24. I C-bus Interface (RIICa) ACKBR Bit (Receive Acknowledge) This bit is used to store the acknowledge bit information received from the receive device in transmit mode. [Setting condition]  When 1 is received as the acknowledge bit with the ICCR2.TRS bit set to 1 [Clearing conditions] ...
Page 738: I 2 C-Bus Function Enable Register (Icfer)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.6 C-bus Function Enable Register (ICFER) Address(es): RIIC0.ICFER 0008 8305h — SCLE NACKE SALE NALE MALE TMOE Value after reset: Symbol Bit Name Description TMOE Timeout Function Enable 0: The timeout function is disabled. 1: The timeout function is enabled.
Page 739 RX13T Group 24. I C-bus Interface (RIICa) NACKE Bit (NACK Reception Transfer Abort Enable) This bit is used to specify whether to continue or discontinue the transfer operation when NACK is received from the slave device in transmit mode. Normally, set this bit to 1. When NACK is received with the NACKE bit set to 1, the next transfer operation is aborted.
Page 740: I 2 C-Bus Status Enable Register (Icser)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.7 C-bus Status Enable Register (ICSER) Address(es): RIIC0.ICSER 0008 8306h HOAE — DIDE — GCAE SAR2E SAR1E SAR0E Value after reset: Symbol Bit Name Description SAR0E Slave Address Register 0 Enable 0: Slave address in registers SARL0 and SARU0 is disabled. 1: Slave address in registers SARL0 and SARU0 is enabled.
Page 741 RX13T Group 24. I C-bus Interface (RIICa) HOAE Bit (Host Address Enable) This bit is used to specify whether to ignore received host address (0001 000b) when the ICMR3.SMBS bit is 1. When this bit is set to 1 while the ICMR3.SMBS bit is 1, if the received slave address matches the host address, the RIIC recognizes the received slave address as the host address independently of the slave addresses set in registers SARLy and SARUy (y = 0 to 2) and performs the receive operation.
Page 742: C-Bus Interrupt Enable Register (Icier)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.8 C-bus Interrupt Enable Register (ICIER) Address(es): RIIC0.ICIER 0008 8307h TEIE NAKIE SPIE STIE ALIE TMOIE Value after reset: Symbol Bit Name Description TMOIE Timeout Interrupt Request Enable 0: Timeout interrupt (TMOI) request is disabled. 1: Timeout interrupt (TMOI) request is enabled.
Page 743 RX13T Group 24. I C-bus Interface (RIICa) TEIE Bit (Transmit End Interrupt Request Enable) This bit is used to enable or disable transmit end interrupt (TEI) requests when the ICSR2.TEND flag is set to 1. An TEI interrupt request is canceled by setting the TEND flag or the TEIE bit to 0. TIE Bit (Transmit Data Empty Interrupt Request Enable) This bit is used to enable or disable transmit data empty interrupt (TXI) requests when the ICSR2.TDRE flag is set to 1.
Page 744: I 2 C-Bus Status Register 1 (Icsr1)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.9 C-bus Status Register 1 (ICSR1) Address(es): RIIC0.ICSR1 0008 8308h — — AAS2 AAS1 AAS0 Value after reset: Symbol Bit Name Description AAS0 Slave Address 0 Detection Flag 0: Slave address 0 is not detected. R/(W) 1: Slave address 0 is detected.
Page 745 RX13T Group 24. I C-bus Interface (RIICa) For 10-bit address format: SARUy.FS bit = 1  When the received slave address does not match a value of (11110b + SARUy.SVA[1:0] bits) with the ICSER.SARyE bit set to 1 (slave address y detection enabled) This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the first byte.
Page 746 RX13T Group 24. I C-bus Interface (RIICa) (host address detection is enabled) This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the first byte.  When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset R01UH0822EJ0100 Rev.1.00 Page 746 of 1041 Jul 31, 2019...
Page 747: I 2 C-Bus Status Register 2 (Icsr2)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.10 C-bus Status Register 2 (ICSR2) Address(es): RIIC0.ICSR2 0008 8309h TDRE TEND RDRF NACKF STOP START TMOF Value after reset: Symbol Bit Name Description TMOF Timeout Detection Flag 0: Timeout is not detected. R/(W) 1: Timeout is detected.
Page 748 RX13T Group 24. I C-bus Interface (RIICa) [Setting conditions] When master arbitration-lost detection is enabled: ICFER.MALE = 1  When the internal SDA output state does not match the SDA0 line level at the rising edge of SCL clock except for the ACK period during data (including slave address) transmission in master transmit mode (when the SDA0 line is driven low while the internal SDA output is at a high level (the SDA0 pin is in the high-impedance state)) ...
Page 749 RX13T Group 24. I C-bus Interface (RIICa) NACKF Flag (NACK Detection Flag) [Setting condition]  When acknowledge is not received (NACK is received) from the receive device in transmit mode with the ICFER.NACKE bit set to 1 (transfer abort enabled) [Clearing conditions] ...
Page 750: Slave Address Register Ly (Sarly) (Y = 0 To 2)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2) Address(es): RIIC0.SARL0 0008 830Ah, RIIC0.SARL1 0008 830Ch, RIIC0.SARL2 0008 830Eh SVA[6:0] SVA0 Value after reset: Symbol Bit Name Description SVA0 10-Bit Address LSB A slave address is set.
Page 751: Slave Address Register Uy (Saruy) (Y = 0 To 2)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2) Address(es): RIIC0.SARU0 0008 830Bh, RIIC0.SARU1 0008 830Dh, RIIC0.SARU2 0008 830Fh — — — — — SVA[1:0] Value after reset: Symbol Bit Name Description 7-Bit/10-Bit Address Format Select 0: The 7-bit address format is selected.
Page 752: I 2 C-Bus Bit Rate Low-Level Register (Icbrl)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.13 C-bus Bit Rate Low-Level Register (ICBRL) Address(es): RIIC0.ICBRL 0008 8310h — — — BRL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 BRL[4:0] Bit Rate Low-Level Period Low-level period of SCL clock b7 to b5 —...
Page 753: I 2 C-Bus Bit Rate High-Level Register (Icbrh)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.14 C-bus Bit Rate High-Level Register (ICBRH) Address(es): RIIC0.ICBRH 0008 8311h — — — BRH[4:0] Value after reset: Symbol Bit Name Description b4 to b0 BRH[4:0] Bit Rate High-Level Period High-level period of SCL clock b7 to b5 —...
Page 754 RX13T Group 24. I C-bus Interface (RIICa) Table 24.5 Examples of ICBRH/ICBRL Settings for Transfer Rate Operating Frequency PCLK (MHz) Transfer 12.5 Rate (kbps) CKS[2:0] ICBRH ICBRL CKS[2:0] ICBRH ICBRL CKS[2:0] ICBRH ICBRL 100b 22 (F6h) 25 (F9h) 101b 13 (EDh) 15 (EFh) 101b 16 (F0h)
Page 755: I 2 C-Bus Transmit Data Register (Icdrt)
RX13T Group 24. I C-bus Interface (RIICa) 24.2.15 C-bus Transmit Data Register (ICDRT) Address(es): RIIC0.ICDRT 0008 8312h Value after reset: When the ICDRT register detects a space in the I C-bus shift register (ICDRS), it transfers the transmit data that has been written to the ICDRT register to the ICDRS register and starts transmitting data in transmit mode.
Page 756: Operation
RX13T Group 24. I C-bus Interface (RIICa) 24.3 Operation 24.3.1 Communication Data Format The I C-bus format consists of 8-bit data and 1-bit acknowledge. The first byte following a start condition or restart condition is an address byte used to specify a slave device with which the master device communicates. The specified slave is valid until a new slave is specified or a stop condition is issued.
Page 757: Initial Settings
RX13T Group 24. I C-bus Interface (RIICa) 24.3.2 Initial Settings Before starting data transmission and reception, initialize the RIIC according to the procedure in Figure 24.5 . Set the ICCR1.ICE bit to 1 (internal reset) after setting the ICCR1.IICRST bit to 1 (RIIC reset) with the ICCR1.ICE bit set to 0 (SCL0 and SDA0 pins in inactive state).
Page 758: Master Transmit Operation
RX13T Group 24. I C-bus Interface (RIICa) 24.3.3 Master Transmit Operation In master transmit operation, the RIIC outputs the SCL clock and transmitted data signals as the master device, and the slave device returns acknowledgments. Figure 24.6 shows an example of usage of master transmission and Figure 24.7 to Figure 24.9 show the timing of operations in master transmission.
Page 759 RX13T Group 24. I C-bus Interface (RIICa) Master transmission [1] Initial settings Initial settings ICCR2.BBSY = 0? [2] Check I C-bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.NACKF = 0? ICSR2.TDRE = 1? [3] Transmit slave address and W (first byte). [4] Check ACK and set transmit data.
Page 760 RX13T Group 24. I C-bus Interface (RIICa) Automatic low-hold (to prevent wrong transmission) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + W) Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF DATA 1 DATA 2 ICDRT...
Page 761: Master Receive Operation
RX13T Group 24. I C-bus Interface (RIICa) SCL0 SDA0 A/NA DATA n-2 DATA n-1 DATA n BBSY Transmit data (DATA n) Transmit data (DATA n-1) TDRE TEND RDRF DATA n-1 ICDRT DATA n ICDRS DATA n-2 DATA n-1 DATA n XXXX (Initial value/final receive data) ICDRR 0 (ACK)
Page 762 RX13T Group 24. I C-bus Interface (RIICa) Because the ICSR2.NACKF flag being 1 at this time indicates that no slave device recognized the address or there was an error in communications, write 1 to the ICCR2.SP bit to issue a stop condition. For master reception from a device with a 10-bit address, start by using master transmission to issue the 10-bit address, and then issue a restart condition.
Page 763 RX13T Group 24. I C-bus Interface (RIICa) Master reception starts Initial settings (1) Initial settings ICCR2.BBSY = 0? (2) Check I C-bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.TDRE = 1? Write the ICDRT register (3) Transmit the slave address followed by R and check ACK.
Page 764 RX13T Group 24. I C-bus Interface (RIICa) Master reception Initial settings [1] Initial settings ICCR2.BBSY = 0? [2] Check I C-bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.TDRE = 1? Write data to ICDRT register [3] Transmit the slave address followed by R and check ACK.
Page 765 RX13T Group 24. I C-bus Interface (RIICa) Automatic low hold Master transmit mode Master receive mode (to prevent wrong transmission) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + R) TDRE Receive data (7-bit address + R) Receive data (DATA 1) TEND RDRF...
Page 766 RX13T Group 24. I C-bus Interface (RIICa) Automatic low hold (WAIT) Automatic low hold (WAIT) SCL0 NACK SDA0 DATA n-2 DATA n-1 DATA n BBSY TDRE Receive data (DATA n-2) Receive data (DATA n-1) Receive data (DATA n) TEND RDRF XXXX (last data for transmission ICDRT [7-bit addresses + R/Upper 10 bits + R])
Page 767: Slave Transmit Operation
RX13T Group 24. I C-bus Interface (RIICa) 24.3.5 Slave Transmit Operation In slave transmit operation, the master device outputs the SCL clock, the RIIC transmits data as a slave device, and the master device returns acknowledgments. Figure 24.15 shows an example of usage of slave transmission and Figure 24.16 and Figure 24.17 show the timing of operations in slave transmission.
Page 768 RX13T Group 24. I C-bus Interface (RIICa) Slave transmission [1] Initial settings Initial settings ICSR2.NACKF = 0? ICSR2.TDRE = 1? Write data to ICDRT register [2], [3] Check ACK bit and set transmit data (Checking of ACK not necessary immediately after address is received) All data transmitted? ICSR2.TEND = 1?
Page 769 RX13T Group 24. I C-bus Interface (RIICa) Slave receive mode Slave transmit mode Automatic low hold (to prevent wrong transmission) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF AASy XXXX (Initial value/last data for transmission)
Page 770: Slave Receive Operation
RX13T Group 24. I C-bus Interface (RIICa) 24.3.6 Slave Receive Operation In slave receive operation, the master device outputs the SCL clock and transmit data, and the RIIC returns acknowledgments as a slave device. Figure 24.18 shows an example of usage of slave reception and Figure 24.19 and Figure 24.20 show the timing of operations in slave reception.
Page 771 RX13T Group 24. I C-bus Interface (RIICa) Automatic low hold (to prevent failure to receive data) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY TDRE Receive data (7-bit address + W) Receive data (DATA 1) TEND RDRF AASy ICDRT XXXX (Initial value/last data for transmission) ICDRS...
Page 772: Scl Synchronization Circuit
RX13T Group 24. I C-bus Interface (RIICa) 24.4 SCL Synchronization Circuit In generation of the SCL clock, the RIIC starts counting out the value for width at high level specified in the ICBRH register when it detects a rising edge on the SCL0 line and drives the SCL0 line low once counting of the width at high level is complete.
Page 773: Sda Output Delay Function
RX13T Group 24. I C-bus Interface (RIICa) 24.5 SDA Output Delay Function The RIIC module incorporates a function for delaying output on the SDA line. The delay can be applied to all output (issuing of the start, restart, and stop conditions, data, and the ACK and NACK signals) on the SDA line. With the SDA output delay function, SDA output is delayed from detection of a falling edge of the SCL signal to ensure that the SDA signal is output within the interval over which the SCL clock is at the low level.
Page 774: Digital Noise Filter Circuit
RX13T Group 24. I C-bus Interface (RIICa) 24.6 Digital Noise Filter Circuit The states of the SCL0 and SDA0 pins are conveyed to the internal circuitry through analog noise-filter and digital noise- filter circuits. Figure 24.23 is a block diagram of the digital noise-filter circuit. The on-chip digital noise-filter circuit of the RIIC consists of four flip-flop circuit stages connected in series and a match- detection circuit.
Page 775: Address Match Detection
RX13T Group 24. I C-bus Interface (RIICa) 24.7 Address Match Detection The RIIC can set three unique slave addresses in addition to the general call address and host address, and also can set 7- bit or 10-bit slave addresses. 24.7.1 Slave-Address Match Detection The RIIC can set three unique slave addresses, and has a slave address detection function for each unique slave address.
Page 776 RX13T Group 24. I C-bus Interface (RIICa) [10-bit address format: Slave reception] SCL0 Upper 2 bits 10-bit slave address (lower 8 bits) Data SDA0 BBSY Address match AASy Receive data (lower addresses) TDRE RDRF Read ICDRR register (Dummy read [lower addresses]) [10-bit address format: Slave transmission] 1 to 8 SCL0...
Page 777: Detection Of The General Call Address
RX13T Group 24. I C-bus Interface (RIICa) 24.7.2 Detection of the General Call Address The RIIC has a facility for detecting the general call address (0000 000b + 0 (write)). This is enabled by setting the ICSER.GCAE bit to 1. If the address received after a start or restart condition is issued is 0000 000b + 1 (read) (start byte), the RIIC recognizes this as the address of a slave device with an “all-zero”...
Page 778: Device-Id Address Detection
RX13T Group 24. I C-bus Interface (RIICa) 24.7.3 Device-ID Address Detection The RIIC module has a facility for detecting device-ID addresses conformant with the I C-bus specification (Rev. 03). When the RIIC receives 1111 100b as the first byte after a start condition or restart condition was issued with the ICSER.DIDE bit set to 1, the RIIC recognizes the address as a device ID, sets the ICSR1.DID flag to 1 on the rising edge of the eighth SCL clock cycle when the following R/W# bit is 0, and then compares the second and subsequent bytes with its own slave address.
Page 779 RX13T Group 24. I C-bus Interface (RIICa) [Device-ID reception] SCL0 SDA0 Address BBSY Slave address match AASy Device-ID match (1111 100b + R) Device-ID match (1111 100b + W) Receive data (7-bit address/lower 10 bits) TDRE RDRF Read ICDRR register (Dummy read [7-bit address/lower 10 bits]) [When address received after a restart condition is detected does not match the device-ID ] SCL0...
Page 780: Host Address Detection
RX13T Group 24. I C-bus Interface (RIICa) 24.7.4 Host Address Detection The RIIC has a function to detect the host address while the SMBus is operating. When the ICSER.HOAE bit is set to 1 while the ICMR3.SMBS bit is 1, the RIIC can detect the host address (0001 000b) in slave receive mode (bits MST and TRS in the ICCR2 register are 00b).
Page 781: Automatic Low-Hold Function For Scl
RX13T Group 24. I C-bus Interface (RIICa) 24.8 Automatic Low-Hold Function for SCL 24.8.1 Function to Prevent Wrong Transmission of Transmit Data If the shift register (ICDRS) is empty when data have not been written to the I C-bus transmit data register (ICDRT) with the RIIC in transmission mode (ICCR2.TRS bit is 1), the SCL0 line is automatically held at the low level over the intervals shown below.
Page 782: Nack Reception Transfer Abort Function
RX13T Group 24. I C-bus Interface (RIICa) 24.8.2 NACK Reception Transfer Abort Function The RIIC has a function to abort transfer operation when NACK is received in transmit mode (ICCR2.TRS bit is 1). This function is enabled when the ICFER.NACKE bit is set to 1 (transfer abort enabled). If the next transmit data has already been written (ICSR2.TDRE flag is 0) when NACK is received, next data transmission at the falling edge of the ninth SCL clock cycle is automatically aborted.
Page 783: Function To Prevent Failure To Receive Data
RX13T Group 24. I C-bus Interface (RIICa) 24.8.3 Function to Prevent Failure to Receive Data If response processing is delayed when receive data (ICDRR) read is delayed for a period of one transfer byte or more with receive data full (ICSR2.RDRF flag is 1) in receive mode (ICCR2.TRS bit is 0), the RIIC holds the SCL0 line low automatically immediately before the next data is received to prevent failure to receive data.
Page 784 RX13T Group 24. I C-bus Interface (RIICa) Automatic low-hold [RDRFS = 0, WAIT = 0] (to prevent failure to receive data) SCL0 SDA0 Data Data Data RDRF Read ICDRR register Read ICDRR register Read ICDRR register [RDRFS = 0, WAIT = 1] Automatic low- Automatic low-hold (WAIT) Automatic low-hold (WAIT)
Page 785: Arbitration-Lost Detection Functions
RX13T Group 24. I C-bus Interface (RIICa) 24.9 Arbitration-Lost Detection Functions In addition to the normal arbitration-lost detection function defined by the I C-bus specification, the RIIC has functions to prevent double-issue of a start condition, to detect arbitration-lost during transmission of NACK, and to detect arbitration-lost in slave transmit mode.
Page 786 RX13T Group 24. I C-bus Interface (RIICa) [When slave addresses conflict] Transmit data mismatch Release SCL/SDA (Arbitration lost) SCL0 SDA0 SCL0 SDA0 Data Data BBSY Address match Address mismatch AASy TDRE Clear AL flag to 0 [When data transmission conflicts after general call address is sent] Transmit data mismatch Release SCL/SDA (Arbitration lost)
Page 787: Function To Detect Loss Of Arbitration During Nack Transmission (Nale Bit)
RX13T Group 24. I C-bus Interface (RIICa) 24.9.2 Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) The RIIC has a function to cause arbitration to be lost if the internal SDA output level does not match the level on the SDA0 line (the high output as the internal SDA output;...
Page 788: Slave Arbitration-Lost Detection (Sale Bit)
RX13T Group 24. I C-bus Interface (RIICa) Condition for arbitration-lost during NACK transmission  When the internal SDA output level does not match the SDA0 line (ACK is received) during transmission of NACK (ICMR3.ACKBT bit = 1) 24.9.3 Slave Arbitration-Lost Detection (SALE Bit) The RIIC has a function to cause arbitration to be lost if the data for transmission (i.e.
Page 789: 24.10 Start Condition/Restart Condition/Stop Condition Issuing Function
RX13T Group 24. I C-bus Interface (RIICa) 24.10 Start Condition/Restart Condition/Stop Condition Issuing Function 24.10.1 Issuing a Start Condition The RIIC issues a start condition when the ICCR2.ST bit is set to 1. When the ST bit is set to 1, a start condition issuance request is made and the RIIC issues a start condition when the ICCR2.BBSY flag is 0 (bus free state).
Page 790: Issuing A Stop Condition
RX13T Group 24. I C-bus Interface (RIICa) 24.10.3 Issuing a Stop Condition The RIIC issues a stop condition when the ICCR2.SP bit is set to 1. When the SP bit is set to 1, a stop condition issuance request is made and the RIIC issues a stop condition when the ICCR2.BBSY flag is 1 (bus busy state) and the ICCR2.MST bit is 1 (master mode).
Page 791: 24.11 Bus Hanging
RX13T Group 24. I C-bus Interface (RIICa) 24.11 Bus Hanging If the clock signals from the master and slave devices go out of synchronization due to noise or other factors, the I C-bus might hang with a fixed level on the SCL0 line and/or SDA0 line. As measures against the bus hanging, the RIIC has a timeout function to detect hanging by monitoring the SCL0 line, a function for the output of an extra SCL clock cycle to release the bus from a hung state due to clock signals being out of synchronization, the RIIC reset function, and internal reset function.
Page 792 RX13T Group 24. I C-bus Interface (RIICa) [Timeout function] Start internal Start internal Start internal Start internal Start internal Start internal counter counter counter counter counter counter Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal counter counter counter...
Page 793: Extra Scl Clock Cycle Output Function
RX13T Group 24. I C-bus Interface (RIICa) 24.11.2 Extra SCL Clock Cycle Output Function In master mode, the RIIC module has a facility for the output of extra SCL clock cycles to release the SDA0 line of the slave device from being held at the low level due to the master being out of synchronization with the slave device. This function is mainly used in master mode to release the SDA0 line of the slave device from the state of being fixed to the low level by including extra cycles of SCL output from the RIIC with single cycles of the SCL clock as the unit if the RIIC cannot issue a stop condition because the slave device is holding the SDA0 line at the low level.
Page 794: Riic Reset And Internal Reset
RX13T Group 24. I C-bus Interface (RIICa) 24.11.3 RIIC Reset and Internal Reset The RIIC module incorporates a function for resetting itself. There are two types of reset. One is referred to as an RIIC reset; this initializes all registers including the ICCR2.BBSY flag. The other is referred to as an internal reset; this releases the RIIC from the slave-address matched state and initializes the internal counter while retaining other settings.
Page 795: 24.12 Smbus Operation
RX13T Group 24. I C-bus Interface (RIICa) 24.12 SMBus Operation The RIIC is available for data communication conforming to the SMBus (Version 2.0). To perform SMBus communication, set the ICMR3.SMBS bit to 1. To use the transfer rate within a range of 10 kbps to 100 kbps of the SMBus specification, set the ICMR1.CKS[2:0] bits, the ICBRH register, and the ICBRL register.
Page 796: Packet Error Code (Pec)
RX13T Group 24. I C-bus Interface (RIICa) SMBus specification : Total clock low-level extended period (slave device) LOW:SEXT : Total clock low-level extended period (master device) LOW:MEXT Start Stop LOW:SEXT LOW:MEXT LOW:MEXT LOW:MEXT LOW:MEXT SCL0 Data 7-bit slave address Data A/NA SDA0 BBSY...
Page 797: 24.13 Interrupt Sources
RX13T Group 24. I C-bus Interface (RIICa) 24.13 Interrupt Sources The RIIC issues four types of interrupt request: transfer error or event generation (arbitration-lost, NACK detection, timeout detection, start condition detection, and stop condition detection), receive data full, transmit data empty, and transmit end.
Page 798: Initialization Of Registers And Functions When A Reset Is Issued Or A Condition Is Detected
RX13T Group 24. I C-bus Interface (RIICa) 24.14 Initialization of Registers and Functions When a Reset is Issued or a Condition is Detected The RIIC can be reset by MCU reset, RIIC reset, and internal reset functions. Table 24.7 lists the reset states of registers and functions when a reset is issued or a condition is detected.
Page 799: 24.15 Usage Notes
RX13T Group 24. I C-bus Interface (RIICa) 24.15 Usage Notes 24.15.1 Setting Module Stop Function Module stop state can be entered or released using module stop control register B (MSTPCRB). The initial setting is for operation of the RIIC to be stopped. RIIC register access is enabled by releasing the module stop state. For details on module stop control register B, refer to section 11, Low Power Consumption .
Page 800: Crc Calculator (Crc)
RX13T Group 25. CRC Calculator (CRC) CRC Calculator (CRC) The CRC (Cyclic Redundancy Check) calculator generates CRC codes. 25.1 Overview Table 25.1 lists the specifications of the CRC calculator, and Figure 25.1 shows a block diagram of the CRC calculator. Table 25.1 CRC Specifications Item...
Page 801: Register Descriptions
RX13T Group 25. CRC Calculator (CRC) 25.2 Register Descriptions 25.2.1 CRC Control Register (CRCCR) Address(es): 0008 8280h DORCL — — — — GPS[1:0] Value after reset: Symbol Bit Name Description b1, b0 GPS[1:0] CRC Generating Polynomial b1 b0 0 0: No calculation is executed. Switching 0 1: 8-bit CRC (X + X + 1)
Page 802: Crc Data Output Register (Crcdor)
RX13T Group 25. CRC Calculator (CRC) 25.2.3 CRC Data Output Register (CRCDOR) Address(es): 0008 8282h Value after reset: CRCDOR is a readable and writable register. Since its initial value is 0000h, rewrite the CRCDOR register to perform calculation using a value other than the initial value.
Page 803: Operation
RX13T Group 25. CRC Calculator (CRC) 25.3 Operation The CRC calculator generates CRC codes for use in LSB first or MSB first transfer. The following shows examples of generating the CRC code for input data (F0h) using the 16-bit CRC generating polynomial (X + 1).
Page 804 RX13T Group 25. CRC Calculator (CRC) 1. 8-bit serial reception (LSB first) CRC code Data Input 2. Write 83h to the CRC control register (CRCCR) CRCCR CRCDOR Clear CRCDOR 3. Write F0h to the CRC data input register (CRCDIR) CRCDIR CRCDOR CRC code generation 4.
Page 805 RX13T Group 25. CRC Calculator (CRC) 1. 8-bit serial reception (MSB first) CRC code Data Input 2. Write 87h to the CRC control register (CRCCR) CRCCR CRCDOR Clear CRCDOR 3. Write F0h to the CRC data input register (CRCDIR) CRCDIR CRCDOR CRC code generation 4.
Page 806: Usage Notes
RX13T Group 25. CRC Calculator (CRC) 25.4 Usage Notes 25.4.1 Module Stop Function Setting Operation of the CRC calculator can be disabled or enabled using the module stop control register B (MSTPCRB). After a reset, the CRC is in the module stop state. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 807: Overview
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 12-Bit A/D Converter (S12ADF) In this section, “PCLK” is used to refer to PCLKB. 26.1 Overview This MCU incorporates one unit of a 12-bit successive approximation A/D converter. The one A/D converter unit (unit 0) provides eight channels for use, and the analog inputs and internal reference voltage for the converter are selectable.
Page 808 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Table 26.1 Specifications of 12-Bit A/D Converter (1/2) Item Description Number of units One unit (S12AD) Input channels Eight channels for S12AD Extended analog function Internal reference voltage A/D conversion method Successive approximation method Resolution 12 bits Conversion time...
Page 809 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Table 26.1 Specifications of 12-Bit A/D Converter (2/2) Item Description  In the modes except double trigger mode and group scan mode, a scan end interrupt request (S12ADI) Interrupt sources can be generated on completion of single scan. ...
Page 810 RX13T Group 26. 12-Bit A/D Converter (S12ADF) S12AD Bus interface AVCC0 12-bit D/A A/D data register A/D control register AVSS0 Interrupt signal (S12ADI, GBADI, GCADI) Internal reference Comparator voltage Control circuit Synchronous trigger (including decoder) (MTU) AN007 Sample and hold circuit Asynchronous trigger (ADTRG0#) AN003...
Page 811 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Table 26.3 Input/Output Pins of 12-Bit A/D Converter Internal Sample & Hold Circuit Unit Pin Name Function for the Pin Unit 0 (S12AD) AN000 Input Analog input pin Incorporated Incorporated AN001 Input Analog input pin Incorporated Incorporated AN002...
Page 812: Register Descriptions
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2 Register Descriptions 26.2.1 A/D Data Registers y (ADDRy) (y = 0 to 7), A/D Data Duplication Register (ADDBLDR), A/D Data Duplication Register A (ADDBLDRA), A/D Data Duplication Register B (ADDBLDRB), A/D Internal Reference Voltage Data Register (ADOCDR) Address(es): S12AD.ADDR0 0008 9020h, S12AD.ADDR1 0008 9022h, S12AD.ADDR2 0008 9024h, S12AD.ADDR3 0008 9026h, S12AD.ADDR4 0008 9028h, S12AD.ADDR5 0008 902Ah, S12AD.ADDR6 0008 902Ch, S12AD.ADDR7 0008 902Eh, S12AD.ADDBLDR 0008 9018h,...
Page 813 RX13T Group 26. 12-Bit A/D Converter (S12ADF)  Flush-right format (in A/D-converted value addition mode and when number of conversions is selected for 16 times) The value added by the A/D-converted value of the same channel is stored in bits 15 to 0. ...
Page 814: A/D Self-Diagnosis Data Register (Adrd)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.2 A/D Self-Diagnosis Data Register (ADRD) Address(es): S12AD.ADRD 0008 901Eh Value after reset: ADRD is a 16-bit read-only register that stores the A/D conversion results based on the 12-bit A/D converter’s self- diagnosis. In addition to the A/D-converted value, the self-diagnosis status is included in. In the ADRD register, the different formats are used depending on the conditions below.
Page 815: A/D Control Register (Adcsr)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.3 A/D Control Register (ADCSR) Address(es): S12AD.ADCSR 0008 9000h TRGE EXTRG DBLE GBADI ADST ADCS[1:0] ADIE — — — DBLANS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 DBLANS[4:0] Double Trigger These bits select one analog input channel for double triggered Channel Select operation.
Page 816 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Table 26.5 Relationship between DBLANS[4:0] Bits Settings and Double Trigger Enabled Channels DBLANS[4:0] Duplication Channel 00000b AN000 00001b AN001 00010b AN002 00011b AN003 00100b AN004 00101b AN005 00110b AN006 00111b AN007 Note: Duplication cannot be selected for the A/D conversion data of self-diagnosis and internal reference voltage. GBADIE Bit (Group B Scan End Interrupt Enable) The GBADIE bit enables or disables group B scan end interrupt in group scan mode.
Page 817 RX13T Group 26. 12-Bit A/D Converter (S12ADF) ADCS[1:0] Bits (Scan Mode Select) The ADCS[1:0] bits select the scan mode. In single scan mode, A/D conversion is performed for the analog inputs selected with the ADANSA0 register in the ascending order of the channel number, and when one cycle of A/D conversion is completed for all the selected channels, the scan conversion is stopped.
Page 818 RX13T Group 26. 12-Bit A/D Converter (S12ADF)  With group priority control operation mode enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit = 1), the ADGSPCR.GBRSCN bit is set to 1 and the scanning of the low-priority group started by a trigger is stopped. Note: When group priority control operation mode has been enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit = 1), do not set the ADST bit to 1.
Page 819: A/D Channel Select Register A0 (Adansa0)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.4 A/D Channel Select Register A0 (ADANSA0) (1) S12AD.ADANSA0 Address(es): 0008 9004h ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 ANSA0 — — — — — — — — Value after reset: Symbol Bit Name Description ANSA000 A/D Conversion Channel Select...
Page 820: A/D Channel Select Register B0 (Adansb0)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.5 A/D Channel Select Register B0 (ADANSB0) (1) S12AD.ADANSB0 Address(es): 0008 9014h ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 ANSB0 — — — — — — — — Value after reset: Symbol Bit Name Description ANSB000 A/D Conversion Channel Select...
Page 821: A/D Channel Select Register C0 (Adansc0)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.6 A/D Channel Select Register C0 (ADANSC0) (1) S12AD.ADANSC0 Address(es): 0008 90D4h ANSC0 ANSC0 ANSC0 ANSC0 ANSC0 ANSC0 ANSC0 ANSC0 — — — — — — — — Value after reset: Symbol Bit Name Description ANSC000 A/D Conversion Channel Select...
Page 822: A/D-Converted Value Addition/Average Function Channel Select Register 0 (Adads0)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.7 A/D-Converted Value Addition/Average Function Channel Select Register 0 (ADADS0) (1) S12AD.ADADS0 Address(es): 0008 9008h ADS00 ADS00 ADS00 ADS00 ADS00 ADS00 ADS00 ADS00 — — — — — — — — Value after reset: Symbol Bit Name Description...
Page 823: A/D-Converted Value Addition/Average Count Select Register (Adadc)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.8 A/D-Converted Value Addition/Average Count Select Register (ADADC) Address(es): S12AD.ADADC 0008 900Ch AVEE — — — — ADC[2:0] Value after reset: Symbol Bit Name Description b2 to b0 ADC[2:0] Addition Count Select 0 0 0: 1-time conversion (no addition; same as normal conversion) 0 0 1: 2-time conversion (addition once) 0 1 0: 3-time conversion (addition twice)* 0 1 1: 4-time conversion (addition three times)
Page 824: A/D Control Extended Register (Adcer)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.9 A/D Control Extended Register (ADCER) Address(es): S12AD.ADCER 0008 900Eh ADRFM DIAGM DIAGL — — — DIAGVAL[1:0] — — — — — — — Value after reset: Symbol Bit Name Description b4 to b0 —...
Page 825 RX13T Group 26. 12-Bit A/D Converter (S12ADF) starts at the fixed voltage value. The DIAGLD bit should be set while the ADCSR.ADST bit is 0. DIAGM Bit (Self-Diagnosis Enable) The DIAGM bit enables or disables self-diagnosis. Self-diagnosis is used to detect a failure of the 12-bit A/D converter. Specifically, one of the internally generated voltage values 0, the reference power supply ×...
Page 826: A/D Conversion Start Trigger Select Register (Adstrgr)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.10 A/D Conversion Start Trigger Select Register (ADSTRGR) Address(es): S12AD.ADSTRGR 0008 9010h — — TRSA[5:0] — — TRSB[5:0] Value after reset: Symbol Bit Name Description b5 to b0 TRSB[5:0] A/D Conversion Start Trigger Select Select the A/D conversion start trigger for group B in for Group B group scan mode.
Page 827 RX13T Group 26. 12-Bit A/D Converter (S12ADF) for details. Table 26.7 lists the selection of A/D conversion start sources selected by the TRSA[5:0] bits. Table 26.6 Selection of A/D Activation Sources by the TRSB[5:0] Bits Module Source Remarks TRSB[5] TRSB[4] TRSB[3] TRSB[2] TRSB[1] TRSB[0] Trigger source deselection state TRGA0N Compare match/input capture from MTU0.TGRA...
Page 828: A/D Conversion Extended Input Control Register (Adexicr)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.11 A/D Conversion Extended Input Control Register (ADEXICR) Address(es): S12AD.ADEXICR 0008 9012h — — — — — — OCSA — — — — — — — OCSAD — Value after reset: Symbol Bit Name Description —...
Page 829: A/D Group C Trigger Select Register (Adgctrgr)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.12 A/D Group C Trigger Select Register (ADGCTRGR) Address(es): S12AD.ADGCTRGR 0008 90D9h GRCE GCADI TRSC[5:0] Value after reset: Symbol Bit Name Description b5 to b0 TRSC[5:0] Group C A/D Conversion Select the A/D conversion start trigger for group C in group scan Start Trigger Select mode.
Page 830 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Table 26.8 Selection of A/D Activation Sources by the TRSC[5:0] Bits Module Source Remarks TRSC[5] TRSC[4] TRSC[3] TRSC[2] TRSC[1] TRSC[0] Trigger source deselection state TRGA0N Compare match/input capture from MTU0.TGRA TRGA1N Compare match/input capture from MTU1.TGRA TRGA2N Compare match/input capture from MTU2.TGRA TRGA3N...
Page 831: A/D Sampling State Register N (Adsstrn) (N = 0 To 7, O)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.13 A/D Sampling State Register n (ADSSTRn) (n = 0 to 7, O) Address(es): S12AD.ADSSTR0 0008 90E0h, S12AD.ADSSTR1 0008 90E1h, S12AD.ADSSTR2 0008 90E2h, S12AD.ADSSTR3 0008 90E3h, S12AD.ADSSTR4 0008 90E4h, S12AD.ADSSTR5 0008 90E5h, S12AD.ADSSTR6 0008 90E6h, S12AD.ADSSTR7 0008 90E7h, S12AD.ADSSTRO 0008 90DFh Value after reset: The ADSSTRn register sets the sampling time for analog input.
Page 832: A/D Sample-And-Hold Circuit Control Register (Adshcr)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.14 A/D Sample-and-Hold Circuit Control Register (ADSHCR) Address(es): S12AD.ADSHCR 0008 9066h — — — — — SHANS[2:0] SSTSH[7:0] Value after reset: Symbol Bit Name Description b7 to b0 SSTSH[7:0] Channel-Dedicated Sample-and-Hold Set the sampling time (4 to 255 states). Circuit Sampling Time Setting b10 to b8 SHANS[2:0]...
Page 833: A/D Disconnection Detection Control Register (Addiscr)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.15 A/D Disconnection Detection Control Register (ADDISCR) Address(es): S12AD.ADDISCR 0008 907Ah — — — ADNDIS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 ADNDIS[4:0] A/D Disconnection b4 ADNDIS[4]: Discharge/precharge selected Detection Assist Setting 0: Discharge 1: Precharge b3 to b0 ADNDIS[3:0]: Discharge/precharge period...
Page 834: A/D Group Scan Priority Control Register (Adgspcr)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.16 A/D Group Scan Priority Control Register (ADGSPCR) Address(es): S12AD.ADGSPCR 0008 9080h GBRSC GBRP LGRRS — — — — — — — — — — — — Value after reset: Symbol Bit Name Description Group Priority Control 0: Operation is without group priority control...
Page 835 RX13T Group 26. 12-Bit A/D Converter (S12ADF) GBRSCN Bit (Low-Priority Group Restart Setting) This bit controls the restarting of scan operation during group priority control. If a scan operation on the low-priority group has been stopped by a priority group trigger input with the GBRSCN bit set to 1, the scan operation is restarted after the scanning of the priority group is completed.
Page 836: A/D Programmable Gain Amplifier Control Register (Adpgacr)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.17 A/D Programmable Gain Amplifier Control Register (ADPGACR) (1) S12AD.ADPGACR Address(es): 0008 91A0h P002E P002S P001E P001S P000E P000S — — — — — — — — — — NAMP NAMP NAMP Value after reset: Symbol Bit Name Description...
Page 837: A/D Programmable Gain Amplifier Gain Setting Register 0 (Adpgags0)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.2.18 A/D Programmable Gain Amplifier Gain Setting Register 0 (ADPGAGS0) (1) S12AD.ADPGAGS0 Address(es): 0008 91A2h — — — — P002GAIN[3:0] P001GAIN[3:0] P000GAIN[3:0] Value after reset: Symbol Bit Name Description b3 to b0 P000GAIN[3:0] PGA P000 Gain Setting The relationship between each setting and the gain is as follows:...
Page 838: Operation
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3 Operation 26.3.1 Scanning Operation In scanning, A/D conversion is performed sequentially on the analog inputs of the specified channels. A scan conversion is performed in three operating modes: single scan mode, continuous scan mode, and group scan mode.
Page 839: Single Scan Mode
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.2 Single Scan Mode 26.3.2.1 Basic Operation (Without Channel-Dedicated Sample-and-Hold Circuits) In basic operation of single scan mode, A/D conversion is performed once on the analog input of the specified channels as below. (1) When the ADCSR.ADST bit is set to 1 (A/D conversion start) by software, or synchronous or asynchronous trigger input, A/D conversion is performed for ANn channels selected by the ADANSA0 register, starting from the channel with the smallest number n.
Page 840: Basic Operation (With Channel-Dedicated Sample-And-Hold Circuits)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.2.2 Basic Operation (With Channel-Dedicated Sample-and-Hold Circuits) When a channel-dedicated sample-and-hold circuit is used, sample-and-hold operations are performed first, and this is followed by A/D conversion once of the analog inputs on all selected channels. The ADSHCR.SHANS[2:0] bits are used to select the channels for which the channel-dedicated sample-and-hold circuits are to be used.
Page 841: Channel Selection And Self-Diagnosis (Without Channel-Dedicated Sample-And-Hold Circuits)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.2.3 Channel Selection and Self-Diagnosis (Without Channel-Dedicated Sample- and-Hold Circuits) When channels and self-diagnosis are selected, A/D conversion is performed once for the reference voltage supplied to the 12-bit A/D converter as below. After that, A/D conversion is performed only once on the analog input of the selected channels.
Page 842: Channel Selection And Self-Diagnosis (With Channel-Dedicated Sample-And-Hold Circuits)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.2.4 Channel Selection and Self-Diagnosis (With Channel-Dedicated Sample-and- Hold Circuits) When channels and self-diagnosis are selected and a channel-dedicated sample-and-hold circuit is used, sample-and-hold operations are performed first, and A/D conversion is performed once for the reference voltage supplied to the 12-bit A/D converter as below.
Page 843: A/D Conversion Of Internal Reference Voltage
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.2.5 A/D Conversion of Internal Reference Voltage A/D conversion of the internal reference voltage is performed in single scan mode as below. All channels should be deselected (by setting the ADANSA0 register bits to all 0 and the ADCSR.DBLE bit to 0). (1) Set the sampling time to 5 μs or longer.
Page 844: A/D Conversion In Double Trigger Mode
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.2.6 A/D Conversion in Double Trigger Mode In single scan mode with double trigger mode, single scan operation started by synchronous trigger is performed twice as below. Self-diagnosis should be deselected, and the internal reference voltage A/D conversion select bit (S12AD.ADEXICR.OCSA) should be set to 0.
Page 845: A/D Conversion In Extended Double Trigger Mode
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.2.7 A/D Conversion in Extended Double Trigger Mode When the double-trigger mode is selected in single-scanning mode, with TRG4AN or TRG4BN selected in the TRSA[5:0] bits of the A/D conversion start trigger select register (ADSTRGR), proceed with single scanning twice as follows.
Page 846 RX13T Group 26. 12-Bit A/D Converter (S12ADF) MTU4.TGRA MTU4.TADCORB MTU4.TCNT MTU4.TADCORA 0000h TRG4AN TRG4BN Synchronous trigger A/D conversion is A/D conversion is executed once. executed once. A/D conversion ADST started A/D conversion time A/D conversion time Channel 3 A/D conversion 1 A/D conversion 2 Waiting for conversion Waiting for conversion...
Page 847: Continuous Scan Mode
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.3 Continuous Scan Mode 26.3.3.1 Basic Operation (Without Channel-Dedicated Sample and-Hold Circuits) In basic operation of continuous scan mode, A/D conversion is performed repeatedly on the analog input of the specified channels as below. In continuous scan mode, the internal reference voltage A/D conversion select bit (S12AD.ADEXICR.OCSA) should be set to 0 (deselected).
Page 848: Basic Operation (With Channel-Dedicated Sample-And-Hold Circuits)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.3.2 Basic Operation (With Channel-Dedicated Sample-and-Hold Circuits) When a channel-dedicated sample-and-hold circuit is used, sample-and-hold operations are performed first, after which the analog inputs on all selected channels are A/D converted as below. The channels for which the channel-dedicated sample-and-hold circuits are to be used can be selected by the ADSHCR.SHANS[2:0] bits.
Page 849: Channel Selection And Self-Diagnosis (Without Channel-Dedicated Sample-And-Hold Circuits)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.3.3 Channel Selection and Self-Diagnosis (Without Channel-Dedicated Sample- and-Hold Circuits) When channels and self-diagnosis are selected at the same time, A/D conversion is first performed for the reference voltage supplied to the 12-bit A/D converter, and then A/D conversion is performed on the analog input of the selected channels, which sequence is repeated as below.
Page 850: Channel Selection And Self-Diagnosis (With Channel-Dedicated Sample-And-Hold Circuits)
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.3.4 Channel Selection and Self-Diagnosis (With Channel-Dedicated Sample-and- Hold Circuits) When channels and self-diagnosis are selected and a channel-dedicated sample-and-hold circuit is used, sample-and-hold operations are performed first, and A/D conversion is performed for the reference voltage supplied to the 12-bit A/D converter as below.
Page 851: Group Scan Mode
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.4 Group Scan Mode 26.3.4.1 Basic Operation Either two (groups A and B) or three (groups A, B, and C) can be selected as the number of the groups to be used in group scan mode.
Page 852: A/D Conversion In Double Trigger Mode
RX13T Group 26. 12-Bit A/D Converter (S12ADF) Timer count TRG4BN event TRG4ABN event TRG4AN event Time Group A scanned TRG4AN Group B scanned TRG4BN Group C scanned TRG4ABN Scan end interrupt Group B Scan end Interrupt Group C Scan end Interrupt Figure 26.13 Example of Operation in Group Scan Mode...
Page 853 RX13T Group 26. 12-Bit A/D Converter (S12ADF) (1) Scanning of group C is started by the TRGA1N trigger from the MTU. (2) When group C scanning is completed, a group C scan interrupt is generated if the ADGCTRGR.GCADIE bit is 1 (interrupt generation upon group C scan completion enabled).
Page 854: Operation Under Group Priority Control
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.4.3 Operation under Group Priority Control Setting the ADGSPCR.PGS bit to 1 in group scan mode makes operation proceed under group priority control. The group priority order is group A > group B > group C. Either two (groups A and B) or three (groups A, B, and C) can be selected as the number of the groups to be used in group scan mode.
Page 855 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Start Are the ADCSR.ADCS[1:0] bits set to 01b (group scan mode)? To disable trigger input, set the ADSTRGR register to 3F3Fh To disable trigger input, set the ADSTRGR.TRSA[5:0] (set the TRSA[5:0] bits and the TRSB[5:0] bits to 3Fh and bits to 3Fh 3Fh, respectively) Are the ADCSR.ADCS[1:0] bits set to 10b...
Page 856 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Table 26.10 Control of Scanning Operations According to the Settings of the ADGSPCR.GBRSCN Bit Scanning Operation Trigger Input ADGSPCR.GBRSCN = 0 ADGSPCR.GBRSCN = 1 When A/D conversion for Input of trigger for group A Trigger input is ineffective.
Page 857 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Table 26.12 Group Priority Operation Setting and Operating Mode for Three Groups (ADGSPCR.PGS = 1, ADGCTRGR.GRCE = 1) ADGSPCR GBRSCN LGRRS GBRP Operation Group priority operation for three groups (groups A, B, and C) ...
Page 858 RX13T Group 26. 12-Bit A/D Converter (S12ADF) (1) Group Priority Operation for Two Groups (ADGSPCR.PGS = 1, ADGCTRGR.GRCE = 0) The following examples 1 to 5 show group priority operation in group scan mode (ADGSPCR.GBRSCN = 1, ADGSPCR.GBRP = 0, ADGSPCR.LGRRS = 0) when channel 0 is selected for group A and channels 1 to 3 are selected for group B.
Page 859 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Operation example 2: Group A trigger input during group B rescan, with rescan setting Figure 26.17 shows an example when a group A trigger is input during rescan operation on group B. If a group A trigger is input, scan for group A starts even while rescan operation is in progress. Scan for group B starts after scan for group A is completed.
Page 860 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Operation example 3: Group B trigger input during group A scan, with rescan setting The following describes an example when a group B trigger is input during scan operation on group A when the ADGPSCR.GBRSCN bit is 1 (scan for the group is restarted after having been discontinued due to group priority operation).
Page 861 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Operation example 4 shows group priority operation in group scan mode (ADGSPCR.GBRSCN = 0, ADGSPCR.GBRP = 0, ADGSPCR.LGRRS = 0) when channel 0 is selected for group A and channels 1 to 3 are selected for group B. Operation example 4: Group A trigger input during group B scan, without rescan setting (1) When a group B trigger input sets the ADCSR.ADST bit to 1 (A/D conversion start), scan for the ANn channels of group B selected in the ADANSB0 register, starts from the channel with the smallest number n.
Page 862 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Operation example 5 shows group priority operation in group scan mode (ADGSPCR.GBRSCN = 1, ADGSPCR.GBRP = 1, ADGSPCR.LGRRS = 0) when channel 0 is selected for group A and channels 1 and 2 are selected for group B. When the ADGCTRGR.GRCE bit is set to 1, single scan mode is continuously operated on group C and scan for group B is started by trigger input.
Page 863 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Group A scanned Group B scanned Group B scanned Group B scanned Group B scanned (Group priority (GBRP=1) (GBRP=1) (GBRP=1) (GBRP=1) operation) Trigger for group A Trigger for group B GBRP bit Scan Started ADST bit Group A Channel 0 (AN000)
Page 864 RX13T Group 26. 12-Bit A/D Converter (S12ADF) (2) Group Priority Operation for Three Groups (ADGSPCR.PGS = 1, ADGCTRGR.GRCE = 1) The following examples 1 to 5 show group priority operation in group scan mode (ADGSPCR.GBRSCN = 1, ADGSPCR.GBRP = 0, ADGSPCR.LGRRS = 1) when channel 0 is selected for group A, channels 1 and 2 are selected for group B, and channels 3 and 4 are selected for group C.
Page 865 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Group A scanned Group B scanned (Group priority Group C scanned (Group priority operation) Group B rescanned Group C rescanned operation) Trigger for group A Trigger for group B Trigger for group C Scan Started (14) ADST bit...
Page 866 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Operation example 2: Priority group trigger input during low-priority group rescan, with rescan setting Figure 26.22 shows an example when a group A trigger is input during rescan operation on group B. If a trigger for the priority groups (groups A and B for group C and group A for group B) is input, scan for the priority group starts even while rescan operation on the low-priority group is in progress.
Page 867 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Operation example 3: Low-priority group trigger input during priority group scan, with rescan setting The following describes an example when a trigger for the low-priority group is input during scan operation on the priority group when the ADGPSCR.GBRSCN bit is 1 (scan for the group is restarted after having been discontinued due to group priority operation).
Page 868 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Group A scanned Group B scanned Group C scanned Trigger for group A Trigger for group B Trigger for group C Scan Started (12) ADST bit Group A Waiting for A/D conversion A1 Waiting for conversion Channel 0 (AN000) conversion...
Page 869 RX13T Group 26. 12-Bit A/D Converter (S12ADF) (7) The ADST bit is automatically cleared to 0 when scan for group A is completed, and the 12-bit A/D converter enters a wait state. Scan for groups C and B is not started until the next trigger corresponding to the group is input. Group A scanned Group B scanned (Group priority...
Page 870 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Operation example 5 shows group priority operation in group scan mode (ADGSPCR.GBRSCN = 1, ADGSPCR.GBRP = 1, ADGSPCR.LGRRS = 1) when channel 0 is selected for group A, channel 1 is selected for group B, and channels 2 and 3 are selected for group C.
Page 871 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Group B scanned Group A scanned Group C rescanned (Group priority (Group priority Group C scanned (GBRP = 1) Group B rescanned Group C scanned (GBRP = 1) (GBRP = 1) operation) operation) Trigger for group A Trigger for group B GBRP bit...
Page 872: Analog Input Sampling Time And Scan Conversion Time
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.5 Analog Input Sampling Time and Scan Conversion Time Figure 26.26 shows the scan conversion timing in single scan mode, in which scan conversion is activated by software or a synchronous trigger. Figure 26.27 shows the scan conversion timing in single scan mode, in which scan conversion is activated by an asynchronous trigger.
Page 873 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Table 26.13 Times for Conversion during Scanning (in Numbers of Cycles of ADCLK and PCLK) Type/Conditions Synchronous Asynchronous Software Item Symbol Trigger (MTU) Trigger Trigger Unit Scan start A/D conversion on The low-priority group is to 3 PCLKB + 6 ADCLK —...
Page 874 RX13T Group 26. 12-Bit A/D Converter (S12ADF) SCAN SPLSH DIAG CONV Asynchronous trigger ADST bit A/D converter Waiting Sampling DIAG conversion A/D conversion processing Figure 26.27 Scan Conversion Timing (Activated by Asynchronous Trigger) R01UH0822EJ0100 Rev.1.00 Page 874 of 1041 Jul 31, 2019...
Page 875: Usage Example Of A/D Data Register Automatic Clearing Function
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.6 Usage Example of A/D Data Register Automatic Clearing Function Setting the ADCER.ACE bit to 1 automatically clears the A/D data registers (ADDRy, ADRD, ADOCDR, ADDBLDR, ADDBLDRA, ADDBLDRB) to 0000h when the A/D data registers (ADDRy, ADRD, ADOCDR, ADDBLDR, ADDBLDRA, ADDBLDRB) are read by the CPU or DTC.
Page 876 RX13T Group 26. 12-Bit A/D Converter (S12ADF) Precharge Precharge control signal Example of the external circuit Discharge control signal Unit 0: AVCC0 R = 1 MΩ Sampling capacitance Analog input Disconnection Note 1. The converted result should be used after fully evaluated because the result data when disconnection occurs varies depending on the external circuit.
Page 877: Starting A/D Conversion With Asynchronous Trigger
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.3.9 Starting A/D Conversion with Asynchronous Trigger The A/D conversion can be started by the input of an asynchronous trigger. To start up the A/D converter by an asynchronous trigger, the A/D conversion start trigger select bits (ADSTRGR.TRSA[5:0]) should be set to 000000b, and a high-level signal should be input to the asynchronous trigger (ADTRG0# pin).
Page 878: Interrupt Sources And Dtc Transfer Requests
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.4 Interrupt Sources and DTC Transfer Requests 26.4.1 Interrupt Requests The 12-bit A/D converter can send scan end interrupt requests S12ADI, GBADI, and GCADI to the CPU. Setting the ADCSR.ADIE bit to 1 and 0 enables and disables an S12ADI interrupt, respectively; similarly, setting the ADCSR.GBADIE bit to 1 and 0 enables and disables a GBADI interrupt, respectively;...
Page 879: Usage Notes
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.6 Usage Notes 26.6.1 Notes on Reading Data Registers The A/D data registers, A/D data duplication registers, A/D data duplication register A, A/D data duplication register B A/D internal reference voltage data register, and A/D self-diagnosis data register should be read in 16-bit units. If a register is read twice in 8-bit units, that is, the higher-order byte and lower-order byte are separately read, the A/D- converted value having been read first may disagree with the A/D-converted value having been read for the second time.
Page 880: A/D Conversion Restarting Timing And Termination Timing
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.6.3 A/D Conversion Restarting Timing and Termination Timing It takes a maximum of six ADCLK cycles for the idle analog unit of the 12-bit A/D converter to be restarted by setting the ADCSR.ADST bit to 1. It takes a maximum of three ADCLK cycles for the operating analog unit of the 12-bit A/D converter to be terminated by setting the ADCSR.ADST bit to 0.
Page 881: Voltage Range Of Analog Power Supply Pins
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.6.9 Voltage Range of Analog Power Supply Pins If this MCU is used with the voltages outside the following ranges, the reliability of the MCU may be affected.  Analog input voltage range Voltage applied to analog input pins AN000 to AN007: AVSS0 ≤...
Page 882: Notes On Noise Prevention
RX13T Group 26. 12-Bit A/D Converter (S12ADF) 26.6.11 Notes on Noise Prevention To prevent the analog input pins (AN000 to AN007) from being destroyed by abnormal voltage such as excessive surge, a capacitor should be inserted between AVCC0 and AVSS0, and a protection circuit should be connected to protect the above analog input pins as shown Figure 26.35 .
Page 883: D/A Converter For Generating Comparator C Reference Voltage (Da)
RX13T Group 27. D/A Converter for Generating Comparator C Reference Voltage (DA) D/A Converter for Generating Comparator C Reference Voltage (DA) 27.1 Overview This MCU includes one channel of 8-bit D/A converter. This D/A converter is used for generating comparator C reference voltage.
Page 884: Register Descriptions
RX13T Group 27. D/A Converter for Generating Comparator C Reference Voltage (DA) 27.2 Register Descriptions 27.2.1 D/A Data Register 0 (DADR0) Address(es): DA.DADR0 0008 80C0h  DADPR.DPSEL bit = 0 (data is right-justified) — — — — — — — —...
Page 885: D/A Control Register (Dacr)
RX13T Group 27. D/A Converter for Generating Comparator C Reference Voltage (DA) 27.2.2 D/A Control Register (DACR) Address(es): DA.DACR 0008 80C4h — DAOE0 — — — — — — Value after reset: Symbol Bit Name Description b4 to b0 — Reserved These bits are read as 1.
Page 886: Operation
RX13T Group 27. D/A Converter for Generating Comparator C Reference Voltage (DA) 27.3 Operation When the DACR.DAOE0 bit is set to 1, D/A converter is enabled and the conversion result is output. An operation example of D/A conversion is shown below. Figure 27.2 shows the timing of this operation. (1) Set the data for D/A conversion in the DADPR.DPSEL bit and the DADR0 register.
Page 887: Usage Notes
RX13T Group 27. D/A Converter for Generating Comparator C Reference Voltage (DA) 27.4 Usage Notes 27.4.1 Module Stop Function Setting Operation of the 8-bit D/A converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the 8-bit D/A converter to be stopped.
Page 888: Comparator C (Cmpc)
RX13T Group 28. Comparator C (CMPC) Comparator C (CMPC) 28.1 Overview Comparator C compares a reference input voltage to an analog input voltage. The comparison result can be read by software and output externally, and an interrupt request can be generated upon any changes to the comparison result.
Page 889 RX13T Group 28. Comparator C (CMPC) Comparator C0 CMPSEL0 CMPSEL1 CMPIOC CMPSEL[3:0] CVRS[1:0] CPOE CMPMON CMPC00 CMPMON0 CMPC01 CMPC02 COMP0 CMPC03 Noise filter CMPC0 interrupt (same value Edge detector CVREFC0 sampled 3 times) request COMP0 level detection signal (to POE) HCMPON CINV CDFS[1:0]...
Page 890 RX13T Group 28. Comparator C (CMPC) Table 28.2 Comparator C Pin Configuration Pin Name Function CMPC00, CMPC01, CMPC02, CMPC03 Input Comparator C0 analog input pins CMPC10, CMPC11, CMPC12, CMPC13 Input Comparator C1 analog input pins CMPC20, CMPC21, CMPC22 Input Comparator C2 analog input pins CVREFC0 Input Reference input voltage pin 0...
Page 891: Register Descriptions
RX13T Group 28. Comparator C (CMPC) 28.2 Register Descriptions 28.2.1 Comparator Control Register (CMPCTL) Address(es): CMPC0.CMPCTL 000A 0C80h, CMPC1.CMPCTL 000A 0CA0h, CMPC2.CMPCTL 000A 0CC0h HCMP CDFS[1:0] CEG[1:0] — CINV Value after reset: Symbol Bit Name Description CINV Comparator Output Polarity Select 0: Comparator output not inverted 1: Comparator output inverted Comparator Output Enable...
Page 892: Comparator Input Select Register (Cmpsel0)
RX13T Group 28. Comparator C (CMPC) 28.2.2 Comparator Input Select Register (CMPSEL0) Address(es): CMPC0.CMPSEL0 000A 0C84h, CMPC1.CMPSEL0 000A 0CA4h, CMPC2.CMPSEL0 000A 0CC4h — — — — CMPSEL[3:0] Value after reset: Symbol Bit Name Description  Comparator C0 b3 to b0 CMPSEL[3:0] Comparator Input Select* 0 0 0 0 : No input 0 0 0 1 : CMPC00 selected...
Page 893: Comparator Reference Voltage Select Register (Cmpsel1)
RX13T Group 28. Comparator C (CMPC) 28.2.3 Comparator Reference Voltage Select Register (CMPSEL1) Address(es): CMPC0.CMPSEL1 000A 0C88h, CMPC1.CMPSEL1 000A 0CA8h, CMPC2.CMPSEL1 000A 0CC8h — — — — — — CVRS[1:0] Value after reset: Symbol Bit Name Description b1, b0 CVRS[1:0] Reference Input Voltage Select b1 b0 0 0: No input...
Page 894: Comparator Output Monitor Register (Cmpmon)
RX13T Group 28. Comparator C (CMPC) 28.2.4 Comparator Output Monitor Register (CMPMON) Address(es): CMPC0.CMPMON 000A 0C8Ch, CMPC1.CMPMON 000A 0CACh, CMPC2.CMPMON 000A 0CCCh CMPM — — — — — — — Value after reset: Symbol Bit Name Description CMPMON0 Comparator Output Monitor Flag 0: Comparator output is 0.
Page 895: Operation
RX13T Group 28. Comparator C (CMPC) 28.3 Operation 28.3.1 Comparator Operation Example Figure 28.2 shows an operation example of the comparator. The COMPn level detection signal (n = 0 to 2) becomes high when the analog input voltage is higher than the reference input voltage, and the COMPn level detection signal becomes low when the analog input voltage is lower than the reference input voltage (when the CMPCTL.CINV bit is 0).
Page 896: Noise Filter
RX13T Group 28. Comparator C (CMPC) 28.3.2 Noise Filter Comparator C contains a noise filter. The sampling clock can be selected by the CMPCTL.CDFS[1:0] bits. The comparator output signal is sampled every sampling clock, and if the same value is sampled three times, that value is determined as the noise filter output at the next sampling clock.
Page 897: Interrupts
RX13T Group 28. Comparator C (CMPC) 28.3.3 Interrupts Comparator C generates an interrupt request upon detecting any changes in the comparison result. When using the CMPCn interrupt, set at least one of bits CMPCTL.CEG[1:0] to 1 (to a value other than 00b (interrupt request is not generated)).
Page 898: Comparator Setting Flowchart
RX13T Group 28. Comparator C (CMPC) 28.3.5 Comparator Setting Flowchart Figure 28.5 shows the flowchart for setting the comparator-related registers. Start  Set D/A converter for generating reference voltage.* Set D/A converter for generating reference voltage (Refer to section 27, D/A Converter for Generating Comparator C Reference Voltage (DA).) Set CMPSEL0.CMPSEL[3:0] ...
Page 899: Usage Notes
RX13T Group 28. Comparator C (CMPC) 28.4 Usage Notes 28.4.1 Module Stop Function Setting Operation of comparator C can be disabled or enabled using module stop control register B (MSTPCRB). After the reset, comparator C is halted. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 900: Data Operation Circuit (Doc)
RX13T Group 29. Data Operation Circuit (DOC) Data Operation Circuit (DOC) 29.1 Overview The data operation circuit (DOC) is used to compare, add, and subtract 16-bit data. Table 29.1 lists the data operation circuit specifications and Figure 29.1 shows a block diagram of the data operation circuit.
Page 901: Register Descriptions
RX13T Group 29. Data Operation Circuit (DOC) 29.2 Register Descriptions 29.2.1 DOC Control Register (DOCR) Address(es): 0008 B080h DOPCF DOPCF DOPCI — — DCSEL OMS[1:0] Value after reset: Symbol Bit Name Description b1, b0 OMS[1:0] Operating Mode Select b1 b0 0: Data comparison mode 1: Data addition mode 0: Data subtraction mode...
Page 902: Doc Data Input Register (Dodir)
RX13T Group 29. Data Operation Circuit (DOC) 29.2.2 DOC Data Input Register (DODIR) Address(es): 0008 B082h Value after reset: DODIR is a 16-bit readable/writable register in which 16-bit data for use in the operations are stored. 29.2.3 DOC Data Setting Register (DODSR) Address(es): 0008 B084h Value after reset: DODSR is a 16-bit readable/writable register.
Page 903: Operation
RX13T Group 29. Data Operation Circuit (DOC) 29.3 Operation 29.3.1 Data Comparison Mode Figure 29.2 shows an example of the steps involved in data comparison mode operation by the data operation circuit. The following is an example of operation when DCSEL is set to 0 (data mismatch is detected as a result of data comparison).
Page 904: Data Addition Mode
RX13T Group 29. Data Operation Circuit (DOC) 29.3.2 Data Addition Mode Figure 29.3 shows an example of the steps involved in data addition mode operation by the data operation circuit. (1) Writing 01b to the DOCR.OMS[1:0] bits selects data addition mode. (2) 16-bit data is set in the DODSR register as the initial value.
Page 905: Data Subtraction Mode
RX13T Group 29. Data Operation Circuit (DOC) 29.3.3 Data Subtraction Mode Figure 29.4 shows an example of the steps involved in data subtraction mode operation by the data operation circuit. (1) Writing 10b to the DOCR.OMS[1:0] bits selects data subtraction mode. (2) 16-bit data is set in the DODSR register as the initial value.
Page 906: Ram
RX13T Group 30. RAM This MCU has an on-chip high-speed static RAM. 30.1 Overview Table 30.1 lists the specifications of the RAM. Table 30.1 Specifications of RAM Item Description RAM capacity 12 Kbytes RAM address RAM0: 0000 0000h to 0000 2FFFh ...
Page 907: Flash Memory (Flash)
Background Operation (BGO) Programs on the ROM can be executed while rewriting the E2 DataFlash. Note 1. Refer to the manual of each serial programmer and “Renesas Flash Programmer Flash memory programming software User’s Manual” for more details.
Page 908: Rom Area And Block Configuration
RX13T Group 31. Flash Memory (FLASH) 31.2 ROM Area and Block Configuration The maximum ROM size of this MCU is 128 Kbytes. The ROM area is divided into blocks. A block is 1-Kbyte area. When executing the block erase command, the memory is erased by the block. Figure 31.1 shows the ROM Area and Block Configuration.
Page 909: E2 Dataflash Area And Block Configuration
RX13T Group 31. Flash Memory (FLASH) 31.3 E2 DataFlash Area and Block Configuration The E2 DataFlash is 4 Kbytes in the MCU. The E2 DataFlash is divided into blocks and erased in block units. Figure 31.2 shows the E2 DataFlash Area and Block Configuration. Data area 1 block = 1 Kbyte Address for E2 DataFlash...
Page 910: Register Descriptions
RX13T Group 31. Flash Memory (FLASH) 31.4 Register Descriptions 31.4.1 E2 DataFlash Control Register (DFLCTL) Address(es): FLASH.DFLCTL 007F C090h — — — — — — — DFLEN Value after reset: Symbol Bit Name Description DFLEN E2 DataFlash Access 0: Access to E2 DataFlash and access to the extra area in P/E mode* Enable disabled 1: Access to E2 DataFlash and access to the extra area in P/E mode*...
Page 911: Flash P/E Mode Entry Register (Fentryr)
RX13T Group 31. Flash Memory (FLASH) 31.4.2 Flash P/E Mode Entry Register (FENTRYR) Address(es): FLASH.FENTRYR 007F FFB2h FENTR FENTR FEKEY[7:0] — — — — — — Value after reset: Symbol Bit Name Description FENTRY0 ROM P/E Mode Entry 0 0: ROM is in read mode. 1: ROM can be placed in P/E mode.
Page 912: Protection Unlock Register (Fpr)
RX13T Group 31. Flash Memory (FLASH) 31.4.3 Protection Unlock Register (FPR) Address(es): FLASH.FPR 007F C0C0h Value after reset: x: Undefined This write-only register is used to protect the FPMCR register from being rewritten inadvertently when the CPU runs out of control. Writing to the FPMCR register is enabled only when the following procedure is used to access the register. Procedure to unlock protection (1) Write A5h to the FPR register.
Page 913: Flash P/E Mode Control Register (Fpmcr)
RX13T Group 31. Flash Memory (FLASH) 31.4.5 Flash P/E Mode Control Register (FPMCR) Address(es): FLASH.FPMCR 007F FF80h FMS2 LVPE — FMS1 RPDIS — FMS0 — Value after reset: Symbol Bit Name Description — Reserved This bit is read as 0. The write value should be 0. FMS0 Flash Operating Mode Select 0 FMS2 FMS1 FMS0...
Page 914: Flash Initial Setting Register (Fisr)
RX13T Group 31. Flash Memory (FLASH) Wait for ROM mode transition wait time 2 (tMS, refer to section 32, Electrical Characteristics ). RPDIS Bit (ROM P/E Disable) This bit is used to disable the execution of ROM programming/erasure with software. LVPE Bit (Low-Voltage P/E Mode Enable) Set this bit to 0 for programming/erasure in high-speed mode, and set this bit to 1 for programming/erasure in middle- speed mode.
Page 915 RX13T Group 31. Flash Memory (FLASH) Table 31.3 Example of FlashIF Clock Frequency Settings FlashIF Clock PCKA[4:0] Bit FlashIF Clock PCKA[4:0] Bit FlashIF Clock PCKA[4:0] Bit Frequency (MHz) Setting Frequency (MHz) Setting Frequency (MHz) Setting 11111b 11110b 11101b 11100b 11011b 11010b 11001b 11000b...
Page 916: Flash Reset Register (Fresetr)
RX13T Group 31. Flash Memory (FLASH) 31.4.7 Flash Reset Register (FRESETR) Address(es): FLASH.FRESETR 007F FF89h FRESE — — — — — — — Value after reset: Symbol Bit Name Description FRESET Flash Reset 0: Flash control circuit reset is released. 1: Flash control circuit is reset.
Page 917: Flash Control Register (Fcr)
RX13T Group 31. Flash Memory (FLASH) 31.4.9 Flash Control Register (FCR) Address(es): FLASH.FCR 007F FF85h OPST STOP — CMD[3:0] Value after reset: Symbol Bit Name Description b3 to b0 CMD[3:0] Software Command Setting 0 0 0 1: Program 0 0 1 1: Blank check 0 1 0 0: Block erase 0 1 0 1: Unique ID read Settings other than above are prohibited.*...
Page 918 RX13T Group 31. Flash Memory (FLASH) When issuing the unique ID read command with this bit set to 1 after reading data from registers FRBH and FRBL, the sequencer ends the read cycle and enters the wait state. When issuing the unique ID read command again with this bit set to 0, the internal address of the sequencer is incremented by 4, and the next data is read.
Page 919: Flash Extra Area Control Register (Fexcr)
RX13T Group 31. Flash Memory (FLASH) 31.4.10 Flash Extra Area Control Register (FEXCR) Address(es): FLASH.FEXCR 007F C0B7h OPST — — — — CMD[2:0] Value after reset: Symbol Bit Name Description b2 to b0 CMD[2:0] Software Command Setting 0 0 1: Start-up area information program 0 1 0: Access window information program Settings other than above are prohibited.* b6 to b3...
Page 920: Flash Processing Start Address Register H (Fsarh)
RX13T Group 31. Flash Memory (FLASH) Writing to the extra area is started by writing 1 to the OPST bit. Do not write to the CMD[2:0] bits while a software command is being executed. 31.4.11 Flash Processing Start Address Register H (FSARH) Address(es): FLASH.FSARH 007F FF84h —...
Page 921: Flash Processing End Address Register H (Fearh)
RX13T Group 31. Flash Memory (FLASH) 31.4.13 Flash Processing End Address Register H (FEARH) Address(es): FLASH.FEARH 007F FF88h — — — — Value after reset: The FEARH register is used to set the end address of the target processing range in the flash memory when a software command is executed.
Page 922: Flash Read Buffer Register H (Frbh)
RX13T Group 31. Flash Memory (FLASH) 31.4.15 Flash Read Buffer Register H (FRBH) Address(es): FLASH.FRBH 007F C0C4h Value after reset: This register is used to store the upper 2 bytes of the 4-byte data (part of the unique ID) that is read from the extra area when unique ID read is executed.
Page 923: Flash Write Buffer Register L (Fwbl)
RX13T Group 31. Flash Memory (FLASH) 31.4.18 Flash Write Buffer Register L (FWBL) Address(es): FLASH.FWBL 007F FF8Ch Value after reset: This register is used to set the lower 16 bits of the data for programming the ROM or the data for programming the E2 DataFlash.
Page 924: Flash Status Register 0 (Fstatr0)
RX13T Group 31. Flash Memory (FLASH) 31.4.19 Flash Status Register 0 (FSTATR0) Address(es): FLASH.FSTATR0 007F FF8Ah EILGLE ILGLER PRGER — — BCERR — ERERR Value after reset: Symbol Bit Name Description ERERR Erase Error Flag 0: Erasure terminates normally. 1: An error occurs during erasure. PRGERR Program Error Flag 0: Programming terminates normally.
Page 925 RX13T Group 31. Flash Memory (FLASH) [Clearing condition]  The next software command is executed. The value read from this flag is undefined when the FCR.STOP bit is set to 1 (processing is forcibly stopped) during blank checking. ILGLERR Flag (Illegal Command Error Flag) This flag indicates the result of executing a software command.
Page 926: Flash Status Register 1 (Fstatr1)
RX13T Group 31. Flash Memory (FLASH) 31.4.20 Flash Status Register 1 (FSTATR1) Address(es): FLASH.FSTATR1 007F FF8Bh EXRDY FRDY — — — — DRRDY — Value after reset: Symbol Bit Name Description — Reserved This bit is read as 0. DRRDY Data Read Ready Flag 0: No valid data in registers FRBH and FRBL 1: Valid data in registers FRBH and FRBL...
Page 927: Flash Error Address Monitor Register H (Feamh)
RX13T Group 31. Flash Memory (FLASH) 31.4.21 Flash Error Address Monitor Register H (FEAMH) Address(es): FLASH.FEAMH 007F C0BAh — — — — Value after reset: This register is used to check the address where the error has occurred if an error occurs during processing of a software command.
Page 928: Flash Start-Up Setting Monitor Register (Fscmr)
RX13T Group 31. Flash Memory (FLASH) 31.4.23 Flash Start-Up Setting Monitor Register (FSCMR) Address(es): FLASH.FSCMR 007F C0B0h — — — — — — — SASMF — — — — — — — — Value set by Value after reset: user* Symbol Bit Name Description...
Page 929: Flash Access Window End Address Monitor Register (Fawemr)
RX13T Group 31. Flash Memory (FLASH) 31.4.25 Flash Access Window End Address Monitor Register (FAWEMR) Address(es): FLASH.FAWEMR 007F C0B4h — — — — — — Value after reset: The value set by the user* Note 1. The value of the blank product is 1. It is set to the same value set in bit 9 to bit 0 in the FWBH register after the access window information program command is executed.
Page 930: Start-Up Program Protection
RX13T Group 31. Flash Memory (FLASH) 31.5 Start-Up Program Protection When rewriting the start-up program * by self-programming, if the rewrite operation is interrupted due to temporary blackout, the start-up program may not be successfully programmed and the user program may not start properly. This problem can be avoided by rewriting the start-up program without erasing the existing start-up program using the start-up program protection.
Page 931: Area Protection
RX13T Group 31. Flash Memory (FLASH) 31.6 Area Protection Area protection enables rewriting only the selected blocks (access window) in the user area and disables rewriting the other blocks during self-programming. The access window cannot be set in the data area. Specify the start address and end address to set the access window.
Page 932: Programming And Erasure
RX13T Group 31. Flash Memory (FLASH) 31.7 Programming and Erasure The ROM and E2 DataFlash can be programmed and erased by changing the mode of the dedicated sequencer for programming and erasure, and by issuing commands for programming and erasure. The mode transitions and commands required to program or erase the ROM and E2 DataFlash are described below.
Page 933: Read Mode
RX13T Group 31. Flash Memory (FLASH) 31.7.1.2 Read Mode Read mode is for high-speed reading of the ROM/E2 DataFlash. Reading from a ROM address for reading can be accomplished in one ICLK clock. (1) ROM/E2 DataFlash Read Mode In this mode, both the ROM and E2 DataFlash are in read mode. The sequencer enters this mode from P/E mode when setting the FPMCR register to 08h, setting the FENTRYR.FENTRYD bit to 0, and setting the FENTRYR.FENTRY0 bit to 0.
Page 934: Transition From Read Mode To P/E Mode
RX13T Group 31. Flash Memory (FLASH) 31.7.2.2 Transition from Read Mode to P/E Mode Switching to ROM P/E mode is required before executing a software command for the ROM. Figure 31.7 shows the Procedure for Transition from ROM/E2 DataFlash Read Mode to ROM P/E Mode. Figure 31.8 shows the Procedure for Transition from ROM/E2 DataFlash Read Mode to E2 DataFlash P/E Mode.
Page 935 RX13T Group 31. Flash Memory (FLASH) Start in ROM/E2 DataFlash read mode FENTRYR register = AA80h Set E2 DataFlash P/E mode OPCCR.OPCM[2:0] bits = 000b? High-speed operating mode Middle-speed operating mode FPR register = A5h FPR register = A5h Set 10h in Set 50h in FPMCR register = 10h FPMCR register = 50h...
Page 936: Transition From P/E Mode To Read Mode
RX13T Group 31. Flash Memory (FLASH) 31.7.2.3 Transition from P/E Mode to Read Mode High-speed reading of the ROM requires switching to ROM/E2 DataFlash read mode. Figure 31.9 shows the Procedure for Transition from ROM P/E Mode to ROM/E2 DataFlash Read Mode. Figure 31.10 shows the Procedure for Transition from E2 DataFlash P/E Mode to ROM/E2 DataFlash Read Mode.
Page 937 RX13T Group 31. Flash Memory (FLASH) Start in E2 DataFlash P/E mode FPR register = A5h Set 08h in FPMCR register = 08h the FPMCR register FPMCR register = F7h FPMCR register = 08h Wait for t FENTRYR register = AA00h FENTRYR register = 0000h? End in ROM/E2 DataFlash read mode...
Page 938: Software Commands
RX13T Group 31. Flash Memory (FLASH) 31.7.3 Software Commands Software commands consist of commands for programming and erasure and commands for programming start-up program area information and access window information. Table 31.4 lists the software commands for use with the flash memory.
Page 939: Software Command Usage
RX13T Group 31. Flash Memory (FLASH) 31.7.4 Software Command Usage This section describes how to use each software command, using flowcharts. 31.7.4.1 Program Figure 31.11 and Figure 31.12 show the procedure to issue the program command. Start in ROM P/E mode FASR.EXS bit = 0 Set programming address in registers FSARH and FSARL...
Page 940 RX13T Group 31. Flash Memory (FLASH) Start in E2 DataFlash P/E mode FASR.EXS bit = 0 Set programming address in registers FSARH and FSARL Set programming data in FWBL register FCR register = 81h FSTATR1.FRDY flag = 1? FCR register = 00h FSTATR1.FRDY flag = 0? FSTATR0.ILGLERR flag = 1 or FSTATR0.PRGERR flag = 1?
Page 941: Block Erase
RX13T Group 31. Flash Memory (FLASH) 31.7.4.2 Block Erase Figure 31.13 and Figure 31.14 show the procedure to issue the block erase command. Start in ROM P/E mode FASR.EXS bit = 0 Set the beginning address of the erasure block in registers FSARH and FSARL Set the last address of the erasure block in registers FEARH and FEARL...
Page 942 RX13T Group 31. Flash Memory (FLASH) Start in E2 DataFlash P/E mode FASR.EXS bit = 0 Set the beginning address of the erasure block in registers FSARH and FSARL Set the last address of the erasure block in registers FEARH and FEARL FCR register = 84h FSTATR1.FRDY flag = 1? FCR register = 00h...
Page 943: Blank Check
RX13T Group 31. Flash Memory (FLASH) 31.7.4.3 Blank Check Figure 31.15 and Figure 31.16 show the procedure to issue the blank check command. Start in ROM P/E mode FASR.EXS bit = 0 Set the blank check start address in registers FSARH and FSARL Set the blank check end address in registers FEARH and FEARL FCR register = 83h...
Page 944 RX13T Group 31. Flash Memory (FLASH) Start in E2 DataFlash P/E mode FASR.EXS bit = 0 Set blank check start address in registers FSARH and FSARL Set blank check end address in registers FEARH and FEARL FCR register = 83h FSTATR1.FRDY flag = 1? FCR register = 00h FSTATR1.FRDY flag = 0?
Page 945: Start-Up Area Information Program/Access Window Information Program
RX13T Group 31. Flash Memory (FLASH) 31.7.4.4 Start-Up Area Information Program/Access Window Information Program Figure 31.17 shows the procedure to issue the start-up area information program command and access window information program command. When the sequencer has directly entered ROM/PE mode from E2 DataFlash access disabled mode, set the DFLCTL.DFLEN bit to 1 at the beginning of the procedure.
Page 946: Unique Id Read
RX13T Group 31. Flash Memory (FLASH) 31.7.4.5 Unique ID Read Figure 31.18 shows the procedure to issue the unique ID read command. Start in ROM P/E mode FASR.EXS bit = 1 FSARH register = 00h FSARL register = 0850h FEARH register = 00h FEARL register = 086Fh FCR register = 85h Issue the unique ID read command.
Page 947: Forced Stop Of Software Commands
RX13T Group 31. Flash Memory (FLASH) 31.7.4.6 Forced Stop of Software Commands Perform the procedure shown in Figure 31.19 to forcibly stop the blank check command or block erase command. When the command processing is forcibly stopped, registers FEAMH and FEAML store the address at the time of the forced stop.
Page 948: Boot Mode
RX13T Group 31. Flash Memory (FLASH) 31.8 Boot Mode The SCI or FINE interface is used in boot mode. Table 31.5 lists the Programmable and Erasable Areas and Peripheral Modules Used in Boot Mode. Table 31.6 lists the I/O Pins Used in Boot Mode. Table 31.5 Programmable and Erasable Areas and Peripheral Modules Used in Boot Mode Boot Mode...
Page 949: Boot Mode (Sci Interface)
RX13T Group 31. Flash Memory (FLASH) 31.8.1 Boot Mode (SCI Interface) The flash memory can be programmed and erased using asynchronous serial communication in boot mode (SCI interface). The user area and data area can be rewritten. When a reset is released while the MD pin is low, the MCU starts in boot mode (SCI interface). Contact the manufacturer for details on the serial programmer.
Page 950: Starting Up In Boot Mode (Sci Interface)
RX13T Group 31. Flash Memory (FLASH) As shown in Figure 31.21 , set the format to 8-bit data, 1 stop bit, no parity, and LSB first to communicate with the serial programmer. Start Stop Figure 31.21 Communication Format Initial communication with the programmer is performed at 9,600 or 19,200 bps. The communication bit rate can be changed after the MCU is connected with the programmer.
Page 951: Boot Mode (Fine Interface)
RX13T Group 31. Flash Memory (FLASH) 31.8.2 Boot Mode (FINE Interface) The flash memory can be programmed and erased using the FINE in boot mode (FINE interface). The user area and data area can be rewritten. Contact the manufacturer for details on the serial programmer. 31.8.2.1 Operating Conditions in Boot Mode (FINE Interface) FINE is used to communicate with the serial programmer in boot mode (FINE Interface).
Page 952: Flash Memory Protection
RX13T Group 31. Flash Memory (FLASH) 31.9 Flash Memory Protection Flash memory protection prevents the flash memory from being read or rewritten by the third party. The boot mode ID code protection is for connecting the serial programmer, and the on-chip debugging emulator ID code protection is for connecting the on-chip debugging emulator.
Page 953: Boot Mode Id Code Protection
RX13T Group 31. Flash Memory (FLASH) 31.9.1.1 Boot Mode ID Code Protection Boot mode ID code protection disables reading and programming of the user area and data area when the serial programmer is connected by the third party. When the control code indicates 45h or 52h (boot mode ID code protection is enabled), the MCU compares 16-byte ID code sent from the serial programmer with the ID code in the user area.
Page 954: On-Chip Debugging Emulator Id Code Protection
RX13T Group 31. Flash Memory (FLASH) Start Boot mode Protection enabled ID code protection enabled/disabled Protection disabled Check received ID codes Not matched/ Erase all blocks retry ID codes do not match in the user area and data area three times consecutively while control code is 45h Erase all blocks in the user area and data area...
Page 955: 31.10 Communication Protocol
RX13T Group 31. Flash Memory (FLASH) 31.10 Communication Protocol This section describes the protocol used in boot mode. When developing a serial programmer, control with this communication protocol. 31.10.1 State Transition in Boot Mode (SCI Interface) Figure 31.26 shows the Boot Mode (SCI Interface) State Transition. Start up in boot mode Bit rate automatic (for SCI interface)
Page 956: Command And Response Configuration
RX13T Group 31. Flash Memory (FLASH) (3) Boot mode ID code authentication state In this state, the MCU accepts the ID code authentication command. When boot mode ID codes do not match, the MCU remains in the boot mode ID code authentication state. Refer to section 31.9.1.1, Boot Mode ID Code Protection for details on boot mode ID code protection.
Page 957: Boot Mode Status Inquiry
RX13T Group 31. Flash Memory (FLASH) 31.10.4 Boot Mode Status Inquiry This command is used to check the current state and which type of an error occurred immediately after a command issued in the boot program. Table 31.12 and Table 31.13 list a state or error that the MCU responds to. The boot mode status inquiry command can be used in the inquiry/setting host command wait state and program/erase host command wait state.
Page 958: Inquiry Commands
RX13T Group 31. Flash Memory (FLASH) 31.10.5 Inquiry Commands Inquiry commands are used to obtain necessary information for sending setting commands, program/erase commands, and read-check commands. Table 31.14 lists the inquiry commands. These commands can only be used in the inquiry/setting host command wait state.
Page 959: Data Area Availability Inquiry
RX13T Group 31. Flash Memory (FLASH) 31.10.5.2 Data Area Availability Inquiry When the MCU receives this command, it sends the result indicating that the data area is available, area protection can be used, and the data area program command is available. Command Response Size...
Page 960: Data Area Information Inquiry
RX13T Group 31. Flash Memory (FLASH) 31.10.5.4 Data Area Information Inquiry When the MCU receives this command, it sends the number of data areas and addresses. Command Number of Response Size areas Area start address Area end address Size (1 byte): Total bytes of data of Number of areas, Area start address, and Area end address (the value is always 09h) Number of areas (1 byte): Number of areas in the data area (the value is always 01h) Area start address (4 bytes): Start address of the data area (the value is always 0010 0000h) Area end address (4 bytes): End address of the data area (the value is always 0010 0FFFh)
Page 961: Setting Commands
RX13T Group 31. Flash Memory (FLASH) 31.10.6 Setting Commands Setting commands are used to configure the settings necessary to execute program/erase commands in the MCU. Table 31.15 lists Setting Commands. These commands can be used only in the inquiry/setting host command wait state. Table 31.15 Setting Commands Command...
Page 962: Operating Frequency Select
RX13T Group 31. Flash Memory (FLASH) 31.10.6.2 Operating Frequency Select This command is used to specify the operating frequency of the MCU and a bit rate for communication with the flash memory programmer. The bit rate selected in this command should be set to a value with error of less than 4% compared to the bit rate obtained by dividing 32 or 8 MHz that corresponds to the operating voltage.
Page 963: Program/Erase Host Command Wait State Transition
RX13T Group 31. Flash Memory (FLASH)  Bit rate selection error A bit rate selection error occurs when the bit rate specified with the operating frequency select command cannot be set to a value with error of less than 4%. When the new bit rate specified with the operating frequency select command is B, and 32 (MHz) or 8 (MHz) corresponding to the operating voltage is Pφ, the bit rate error is calculated by the following formula: P ...
Page 964: Id Code Authentication Command
RX13T Group 31. Flash Memory (FLASH) 31.10.7 ID Code Authentication Command This command is used for ID code authentication when boot mode ID code protection is enabled. Table 31.16 lists ID code authentication command. This command can be used only in the boot mode ID code authentication state.
Page 965: Program/Erase Commands
RX13T Group 31. Flash Memory (FLASH) 31.10.8 Program/Erase Commands Program/erase commands are used to program or erase the user area or data area based on the response to inquiry commands. Table 31.17 lists commands used in each of the program/erase host command wait state, program wait state, and erase wait state.
Page 966: Program
RX13T Group 31. Flash Memory (FLASH) 31.10.8.2 Program This command is used to program the specified data to the user area or data area. Set the lower 8 bits to 0 for the program address selected in this command. When the data length is shorter than 256 bytes, the data cannot be programmed. Fill the gaps with FFh.
Page 967: Data Area Program
RX13T Group 31. Flash Memory (FLASH) 31.10.8.3 Data Area Program This command is used to program the specified data to the data area. Set the lower 2 bits to 0 for the program address selected in this command. When the data length is shorter than 4 bytes, the data cannot be programmed. Fill the gaps with FFh.
Page 968: Erase Preparation
RX13T Group 31. Flash Memory (FLASH) 31.10.8.4 Erase Preparation This command is used to prepare for accepting the block erase command. When the MCU receives this command, it recognizes that an instruction to prepare for the erase command is issued from the host. Then, the MCU enters the erase wait state, where only the block erase command can be accepted, and sends a response (06h).
Page 969: Read-Check Commands
RX13T Group 31. Flash Memory (FLASH) 31.10.9 Read-Check Commands Read-check commands are used to read data or check whether data is programmed in the user area or data area in the MCU based on the response to inquiry commands. Table 31.19 lists read-check commands used in the program/erase host command wait state. Table 31.19 Read-Check Commands Command...
Page 970: User Area Checksum
RX13T Group 31. Flash Memory (FLASH) Response Read size Read data Read size (4 bytes): Size of Data that is read (in bytes) Read data (n bytes): Data read from the specified range (n = read size) SUM (1 byte): Value that is calculated so the sum of response data is 00h Error response Error Error (1 byte): Error code...
Page 971: Data Area Checksum
RX13T Group 31. Flash Memory (FLASH) 31.10.9.3 Data Area Checksum This command used to obtain the checksum of the entire data area. When the MCU receives this command, it adds data from the start address to the end address in bytes in the data area, and sends the calculated result (checksum) as a response.
Page 972: Data Area Blank Check
RX13T Group 31. Flash Memory (FLASH) 31.10.9.5 Data Area Blank Check This command is used to check whether data is programmed in the user area. When the MCU receives this command, it checks whether there is programmed data in the entire user area. If there is no programmed data, the MCU sends a response (06h).
Page 973: Access Window Read
RX13T Group 31. Flash Memory (FLASH) Response Error response Error Error (1 byte): Error code 11h: SUM error 2Ah: Address error (specified address is not in the area) 53h: Program error (access window cannot be set) 31.10.9.7 Access Window Read This command is used to check the set range of the access window.
Page 974: Serial Programmer Operation In Boot Mode (Sci Interface)
RX13T Group 31. Flash Memory (FLASH) 31.11 Serial Programmer Operation in Boot Mode (SCI Interface) The following describes the procedure for the serial programmer to program/erase the user area and data area in boot mode (SCI Interface). 1. Automatically adjust the bit rate 2.
Page 975: Bit Rate Automatic Adjustment Procedure
RX13T Group 31. Flash Memory (FLASH) 31.11.1 Bit Rate Automatic Adjustment Procedure The MCU measures the low width of data 00h that is sent from the serial programmer at 9,600 or 19,200 bps to automatically adjust the bit rate. At least 1 ms between commands Transmission to the MCU...
Page 976: Procedure To Receive The Mcu Information
RX13T Group 31. Flash Memory (FLASH) 31.11.2 Procedure to Receive the MCU Information Procedure to send inquiry commands, and receive the information necessary to send setting commands, program/erase commands, and read-check commands is as follows. (1) Send a support device inquiry command (20h) to check what type of endianness the MCU supports. The MCU returns all device codes and series names that it supports.
Page 977: Procedure To Select The Device And Change The Bit Rate
RX13T Group 31. Flash Memory (FLASH) 31.11.3 Procedure to Select the Device and Change the Bit Rate Procedure to select the device to connect with the serial programmer and to change the bit rate for communication is as follows. (1) Send the device select command (10h). Select the device code according to the endian of developed software. (2) Send the operating frequency select command (3Fh) to change the communication bit rate from 9,600 or 19,200 bps.
Page 978: Procedure For Transition To The Program/Erase Host Command Wait State
RX13T Group 31. Flash Memory (FLASH) 31.11.4 Procedure for Transition to the Program/Erase Host Command Wait State Send the program/erase host command wait state transition command to perform program/erase operations. The MCU sends a response according to whether boot mode ID code protection is enabled or disabled. (1) When boot mode ID code protection is disabled, the MCU sends a response (06h), and enters the program/erase host command wait state.
Page 979: Procedure To Unlock Boot Mode Id Code Protection
RX13T Group 31. Flash Memory (FLASH) 31.11.5 Procedure to Unlock Boot Mode ID Code Protection Send the ID code check command to unlock boot mode ID code protection. (1) When ID codes match, the MCU enters the program/erase host command wait state. Data in the user area and data area are not erased.
Page 980: Procedure To Erase The User Area And Data Area
RX13T Group 31. Flash Memory (FLASH) 31.11.6 Procedure to Erase the User Area and Data Area Procedure to erase blocks that are programmed in the user area and data area to program a user program and data is as follows. (1) Send an erase preparation command (48h).
Page 981: Procedure To Program The User Area And Data Area
RX13T Group 31. Flash Memory (FLASH) 31.11.7 Procedure to Program the User Area and Data Area Procedure to program a user program and data in the user area and data area is as follows. (1) Send the user/data area program preparation command (43h). (2) Send the program command (50h) or the data area program command (51h).
Page 982: Procedure To Check Data In The User Area
RX13T Group 31. Flash Memory (FLASH) 31.11.8 Procedure to Check Data in the User Area Procedure to read and check, checksum, and blank check the user area to check the programmed data in the user area is as follows. (1) The read and check operation is used to read data in the user area and compare the read data with the programmed data to check if the program operation is performed successfully.
Page 983: Procedure To Check Data In The Data Area
RX13T Group 31. Flash Memory (FLASH) 31.11.9 Procedure to Check Data in the Data Area Procedure to read and check, checksum, and blank check the data area to check the programmed data in the data area is as follows. (1) The read and check operation is used to read data in the data area and compare the read data with the programmed data to check if the program operation is performed successfully.
Page 984: Procedure To Set The Access Window In The User Area
RX13T Group 31. Flash Memory (FLASH) 31.11.10 Procedure to Set the Access Window in the User Area Procedure to set the access window to avoid unintentionally rewriting the user area during the self-programming is as follows. (1) Send the access window program command (74h) to set the access window settings. (2) Send the access window read command (73h) to confirm the access window settings.
Page 985: 31.12 Rewriting By Self-Programming
RX13T Group 31. Flash Memory (FLASH) 31.12 Rewriting by Self-Programming 31.12.1 Overview The MCU supports rewriting of the flash memory by the user program. The ROM and E2 DataFlash can be rewritten by preparing a routine to rewrite the flash memory (flash rewrite routine) in the user program. When rewriting the E2 DataFlash, the BGO can be used to execute the flash rewrite routine on the ROM.
Page 986: 31.13 Usage Notes
RX13T Group 31. Flash Memory (FLASH) 31.13 Usage Notes (1) Access the Block Where Erase Operation is Forcibly Stopped When forcibly stopping an erase operation, data in the block where the erase operation is aborted is undefined. To avoid malfunctions caused by reading undefined data, do not execute instructions or read data in the block where an erase operation is forcibly stopped.
Page 987: 31.14 Usage Notes In Boot Mode
RX13T Group 31. Flash Memory (FLASH) 31.14 Usage Notes in Boot Mode (1) Notes on Communication Errors in Boot Mode When communication with the MCU cannot be performed properly, reset and start up in boot mode again. (2) Notes on Power Supply Voltage in Boot Mode (SCI Interface) When the bit rate exceeds 500 kbps in boot mode (SCI Interface), use a voltage that is 3.0 V or higher.
Page 988: Electrical Characteristics
RX13T Group 32. Electrical Characteristics Electrical Characteristics 32.1 Absolute Maximum Ratings Table 32.1 Absolute Maximum Ratings Conditions: VSS = AVSS0 = 0 V Item Symbol Value Unit Power supply voltage –0.3 to +6.5 Input voltage P40 to P47 –0.3 to AVCC0+0.3 PB1, PB2 (5-V tolerant) –0.3 to +6.5 Other than above...
Page 989: Dc Characteristics
RX13T Group 32. Electrical Characteristics 32.3 DC Characteristics Table 32.4 DC Characteristics (1) Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = VCC to 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Test Item Symbol Min.
Page 990 RX13T Group 32. Electrical Characteristics Table 32.6 DC Characteristics (3) Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = VCC to 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Test Item Symbol Typ.* Max. Unit Conditions Supply...
Page 991 RX13T Group 32. Electrical Characteristics Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up resistors are disabled. Note 2. Peripheral module clocks are stopped. This does not include BGO operation. The clock source is the PLL. FCLK and PCLK are set for division by 64.
Page 992 RX13T Group 32. Electrical Characteristics Ta = 105°C Ta = 85°C Ta = 105°C Ta = 85°C Ta = 55°C Ta = 55°C Ta = 25°C Ta = 25°C VCC (V) Ta = 25°C Ta = 55°C Ta = 85°C Ta = 105°C Ta = 25°C Ta = 55°C...
Page 993 G-version product Note: Please contact a Renesas Electronics sales office for information on the derating of the G-version product. Derating is the systematic reduction of load for the sake of improved reliability. Note 1. Total power dissipated by the entire chip (including output currents) Table 32.9...
Page 994 RX13T Group 32. Electrical Characteristics Table 32.11 DC Characteristics (8) Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = VCC to 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C The ripple voltage must meet the allowable ripple frequency f within the range between the VCC upper limit (5.5 V) and r (VCC) lower limit (2.7 V).
Page 995 RX13T Group 32. Electrical Characteristics Table 32.13 Output Values of Voltage (1) Conditions: VCC = 2.7 V to 4.0 V, AVCC0 = VCC to 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Item Symbol Min. Max.
Page 996: Normal I/O Pin Output Voltage Characteristics
RX13T Group 32. Electrical Characteristics 32.3.1 Normal I/O Pin Output Voltage Characteristics Table 32.15 Normal I/O Pin V Voltage Characteristics (Reference Data) Conditions: VCC = AVCC0 = 3.3 V, VSS = AVSS0 = 0 V, Ta = 25°C Item Symbol Min. Typ. Max. Unit Test Conditions High-level...
Page 997 RX13T Group 32. Electrical Characteristics Table 32.17 Normal I/O Pin V Voltage Characteristics (Reference Data) Conditions: VCC = AVCC0 = 3.3 V, VSS = AVSS0 = 0 V, Ta = 25°C Item Symbol Min. Typ. Max. Unit Test Conditions Low-level All output pins Normal output mode —...
Page 998: Ac Characteristics
RX13T Group 32. Electrical Characteristics 32.4 AC Characteristics 32.4.1 Clock Timing Table 32.19 Operating Frequency Value (High-Speed Operating Mode) Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = VCC to 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Item Symbol...
Page 999 RX13T Group 32. Electrical Characteristics Table 32.21 Clock Timing Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = VCC to 5.5 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Item Symbol Min. Typ. Max. Unit Test Conditions EXTAL external clock input cycle time —...
Page 1000 RX13T Group 32. Electrical Characteristics MOSCCR.MOSTP MAINOSC Main clock oscillator output Figure 32.5 Main Clock Oscillation Start Timing LOCOCR.LCSTP LOCO LOCO clock oscillator output Figure 32.6 LOCO Clock Oscillation Start Timing ILOCOCR.ILCSTP ILOCO IWDT-dedicated clock oscillator output Figure 32.7 IWDT-Dedicated Clock Oscillation Start Timing RES# Internal reset RESWT...

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Renesas RX100 Series User Manual

Features

Overview

Cpu

Operating Modes

Address Space

I/O Registers

Resets

Option-Setting Memory (OFSM)

Voltage Detection Circuit (Lvdab)

Clock Generation Circuit

Clock Frequency Accuracy Measurement Circuit (CAC)

Low Power Consumption

Register Write Protection Function

Exception Handling

Interrupt Controller (Icub)

Buses

Data Transfer Controller (Dtcb)

Quick Links

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Summary of Contents for Renesas RX100 Series