I 2 C-Bus Mode Register 2 (Icmr2) - Renesas RX100 Series User Manual

RX13T Group
2
24.2.4 I C-bus Mode Register 2 (ICMR2)
Address(es): RIIC0.ICMR2 0008 8303h
b7 b6
DLCS
0 0
Value after reset:
Bit Symbol Bit Name
b0 TMOS Timeout Detection Time Select
b1 TMOL Timeout L Count Control
b2 TMOH Timeout H Count Control
b3 — Reserved
b6 to b4 SDDL[2:0] SDA Output Delay Counter
b7 DLCS SDA Output Delay Clock Source
Select
Note 1. The DLCS bit setting of 1 (IICφ/2) only becomes valid when SCL pin is low. When SCL pin is high, the DLCS bit setting of 1
becomes invalid and the clock source becomes the internal reference clock (IICφ).
TMOS Bit (Timeout Detection Time Select)
This bit is used to select long mode or short mode for the timeout detection time when the timeout function is enabled
(ICFER.TMOE bit is 1). When this bit is set to 0, long mode is selected. When this bit is set to 1, short mode is selected.
In long mode, the timeout detection internal counter functions as a 16-bit counter. In short mode, the counter functions as
a 14-bit counter. While the SCL0 line is in the state that enables this counter as specified by bits TMOH and TMOL, the
counter counts up in synchronization with the internal reference clock (IICφ) as a count source.
For details on the timeout function, refer to section 24.11.1, Timeout Function .
TMOL Bit (Timeout L Count Control)
This bit is used to enable or disable the internal counter of the timeout function to count up while the SCL0 line is held
low when the timeout function is enabled (ICFER.TMOE bit is 1).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
SDDL[2:0] — TMOH TMOL TMOS
0 0 0 1
b1 b0
1 0
Description
0: Long mode is selected.
1: Short mode is selected.
0: Count-up is disabled while the SCL0 line is at a low level.
1: Count-up is enabled while the SCL0 line is at a low level.
0: Count-up is disabled while the SCL0 line is at a high level.
1: Count-up is enabled while the SCL0 line is at a high level.
This bit is read as 0. The write value should be 0.
 When ICMR2.DLCS bit is 0 (IICφ)
b6 b4
0 0 0: No output delay
0 0 1: 1 IICφ cycle
0 1 0: 2 IICφ cycles
0 1 1: 3 IICφ cycles
1 0 0: 4 IICφ cycles
1 0 1: 5 IICφ cycles
1 1 0: 6 IICφ cycles
1 1 1: 7 IICφ cycles
 When ICMR2.DLCS bit is 1 (IICφ/2)
b6 b4
0 0 0: No output delay
0 0 1: 1 or 2 IICφ cycles
0 1 0: 3 or 4 IICφ cycles
0 1 1: 5 or 6 IICφ cycles
1 0 0: 7 or 8 IICφ cycles
1 0 1: 9 or 10 IICφ cycles
1 1 0: 11 or 12 IICφ cycles
1 1 1: 13 or 14 IICφ cycles
0: The internal reference clock (IICφ) is selected as the clock
source of the SDA output delay counter.
1: The internal reference clock divided by 2 (IICφ/2) is selected as
the clock source of the SDA output delay counter.*
2
24. I C-bus Interface (RIICa)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
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