Description Of Buses; Cpu Buses; Memory Buses; Internal Main Buses - Renesas RX100 Series User Manual

RX13T Group
15.2

Description of Buses

15.2.1

CPU Buses

The CPU buses consist of the instruction and operand buses, which are connected to internal main bus 1. As the names
suggest, the instruction bus is used to fetch instructions for the CPU, while the operand bus is used for operand access.
Connection of the instruction and operand buses to RAM and ROM provides the CPU with direct access to these areas,
i.e. access is not via internal main bus 1. However, only reading is possible in direct access to ROM by the CPU;
programming and erasure are handled via an internal peripheral bus.
Bus requests for instruction fetching and operand access are arbitrated through internal main bus 1. The order of priority
is operand access then instruction fetching.
If instruction fetching and operand access are requested for different buses (memory bus 1, memory bus 2, and internal
main bus 1), the bus-access operations can proceed simultaneously. For example, parallel access to ROM and RAM is
possible.
15.2.2

Memory Buses

The memory buses consist of memory bus 1 and memory bus 2. RAM is connected to memory bus 1 and ROM is
connected to memory bus 2. Requests for bus mastership from the CPU buses (instruction fetching and operand) and
internal main bus 2 are arbitrated through memory buses 1 and 2.
The priority order of CPU bus and internal main bus 2 can be set using the memory bus 1 (RAM) priority control bits
(BPRA[1:0]) and memory bus 2 (ROM) priority control bits (BPRO[1:0]) in the bus priority control register (BUSPRI)
for the corresponding memory buses. When the priority order is fixed, internal main bus 2 has priority over the CPU bus
(operand over instruction fetching). When the priority order is toggled, the bus for which a request has been accepted has
lower priority.
15.2.3

Internal Main Buses

The internal main buses consist of a bus for use by the CPU (internal main bus 1) and a bus for use by the other bus-
master modules, i.e. the DTC (internal main bus 2).
Bus requests for instruction fetching and operand access are arbitrated through internal main bus 1. The order of priority
is operand access then instruction fetching.
Requests for bus mastership from the DTC is arbitrated by internal main bus 2. The order of priority is as shown in Table
15.3 .
If the CPU and another bus master are requesting access to different buses (on-chip memory, internal peripheral buses 1
to 3 and 6), the respective bus-access operations can proceed simultaneously.
However, when the CPU executes the XCHG instruction, requests for bus access from masters other than the CPU are
not accepted until data transfer for the XCHG instruction is completed regardless of the bus priority control register
(BUSPRI) setting. Furthermore, requests for bus access from masters other than the DTC are not accepted during reading
and writing-back of transfer control information for the DTC.
Table 15.3 Order of Priority for Bus Masters
Priority Bus Master
High DTC
CPU
Low
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
15. Buses
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